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Documentation / virtual / kvm / devices / xics.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:05 EST.

1	XICS interrupt controller
2	
3	Device type supported: KVM_DEV_TYPE_XICS
4	
5	Groups:
6	  KVM_DEV_XICS_SOURCES
7	  Attributes: One per interrupt source, indexed by the source number.
8	
9	This device emulates the XICS (eXternal Interrupt Controller
10	Specification) defined in PAPR.  The XICS has a set of interrupt
11	sources, each identified by a 20-bit source number, and a set of
12	Interrupt Control Presentation (ICP) entities, also called "servers",
13	each associated with a virtual CPU.
14	
15	The ICP entities are created by enabling the KVM_CAP_IRQ_ARCH
16	capability for each vcpu, specifying KVM_CAP_IRQ_XICS in args[0] and
17	the interrupt server number (i.e. the vcpu number from the XICS's
18	point of view) in args[1] of the kvm_enable_cap struct.  Each ICP has
19	64 bits of state which can be read and written using the
20	KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu.  The 64 bit
21	state word has the following bitfields, starting at the
22	least-significant end of the word:
23	
24	* Unused, 16 bits
25	
26	* Pending interrupt priority, 8 bits
27	  Zero is the highest priority, 255 means no interrupt is pending.
28	
29	* Pending IPI (inter-processor interrupt) priority, 8 bits
30	  Zero is the highest priority, 255 means no IPI is pending.
31	
32	* Pending interrupt source number, 24 bits
33	  Zero means no interrupt pending, 2 means an IPI is pending
34	
35	* Current processor priority, 8 bits
36	  Zero is the highest priority, meaning no interrupts can be
37	  delivered, and 255 is the lowest priority.
38	
39	Each source has 64 bits of state that can be read and written using
40	the KVM_GET_DEVICE_ATTR and KVM_SET_DEVICE_ATTR ioctls, specifying the
41	KVM_DEV_XICS_SOURCES attribute group, with the attribute number being
42	the interrupt source number.  The 64 bit state word has the following
43	bitfields, starting from the least-significant end of the word:
44	
45	* Destination (server number), 32 bits
46	  This specifies where the interrupt should be sent, and is the
47	  interrupt server number specified for the destination vcpu.
48	
49	* Priority, 8 bits
50	  This is the priority specified for this interrupt source, where 0 is
51	  the highest priority and 255 is the lowest.  An interrupt with a
52	  priority of 255 will never be delivered.
53	
54	* Level sensitive flag, 1 bit
55	  This bit is 1 for a level-sensitive interrupt source, or 0 for
56	  edge-sensitive (or MSI).
57	
58	* Masked flag, 1 bit
59	  This bit is set to 1 if the interrupt is masked (cannot be delivered
60	  regardless of its priority), for example by the ibm,int-off RTAS
61	  call, or 0 if it is not masked.
62	
63	* Pending flag, 1 bit
64	  This bit is 1 if the source has a pending interrupt, otherwise 0.
65	
66	Only one XICS instance may be created per VM.
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