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Documentation / devicetree / bindings / pinctrl / rockchip,pinctrl.txt




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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:55 EST.

1	* Rockchip Pinmux Controller
2	
3	The Rockchip Pinmux Controller, enables the IC
4	to share one PAD to several functional blocks. The sharing is done by
5	multiplexing the PAD input/output signals. For each PAD there are several
6	muxing options with option 0 being the use as a GPIO.
7	
8	Please refer to pinctrl-bindings.txt in this directory for details of the
9	common pinctrl bindings used by client devices, including the meaning of the
10	phrase "pin configuration node".
11	
12	The Rockchip pin configuration node is a node of a group of pins which can be
13	used for a specific device or function. This node represents both mux and
14	config of the pins in that group. The 'pins' selects the function mode(also
15	named pin mode) this pin can work on and the 'config' configures various pad
16	settings such as pull-up, etc.
17	
18	The pins are grouped into up to 5 individual pin banks which need to be
19	defined as gpio sub-nodes of the pinmux controller.
20	
21	Required properties for iomux controller:
22	  - compatible: should be
23			"rockchip,rv1108-pinctrl":  for Rockchip RV1108
24			"rockchip,rk2928-pinctrl":  for Rockchip RK2928
25			"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
26			"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
27			"rockchip,rk3188-pinctrl":  for Rockchip RK3188
28			"rockchip,rk3228-pinctrl":  for Rockchip RK3228
29			"rockchip,rk3288-pinctrl":  for Rockchip RK3288
30			"rockchip,rk3328-pinctrl":  for Rockchip RK3328
31			"rockchip,rk3368-pinctrl":  for Rockchip RK3368
32			"rockchip,rk3399-pinctrl":  for Rockchip RK3399
33	
34	  - rockchip,grf: phandle referencing a syscon providing the
35		 "general register files"
36	
37	Optional properties for iomux controller:
38	  - rockchip,pmu: phandle referencing a syscon providing the pmu registers
39		 as some SoCs carry parts of the iomux controller registers there.
40		 Required for at least rk3188 and rk3288. On the rk3368 this should
41		 point to the PMUGRF syscon.
42	
43	Deprecated properties for iomux controller:
44	  - reg: first element is the general register space of the iomux controller
45		 It should be large enough to contain also separate pull registers.
46		 second element is the separate pull register space of the rk3188.
47		 Use rockchip,grf and rockchip,pmu described above instead.
48	
49	Required properties for gpio sub nodes:
50	  - compatible: "rockchip,gpio-bank"
51	  - reg: register of the gpio bank (different than the iomux registerset)
52	  - interrupts: base interrupt of the gpio bank in the interrupt controller
53	  - clocks: clock that drives this bank
54	  - gpio-controller: identifies the node as a gpio controller and pin bank.
55	  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
56	    binding is used, the amount of cells must be specified as 2. See generic
57	    GPIO binding documentation for description of particular cells.
58	  - interrupt-controller: identifies the controller node as interrupt-parent.
59	  - #interrupt-cells: the value of this property should be 2 and the interrupt
60	    cells should use the standard two-cell scheme described in
61	    bindings/interrupt-controller/interrupts.txt
62	
63	Deprecated properties for gpio sub nodes:
64	  - compatible: "rockchip,rk3188-gpio-bank0"
65	  - reg: second element: separate pull register for rk3188 bank0, use
66		 rockchip,pmu described above instead
67	
68	Required properties for pin configuration node:
69	  - rockchip,pins: 3 integers array, represents a group of pins mux and config
70	    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
71	    The MUX 0 means gpio and MUX 1 to N mean the specific device function.
72	    The phandle of a node containing the generic pinconfig options
73	    to use, as described in pinctrl-bindings.txt in this directory.
74	
75	Examples:
76	
77	#include <dt-bindings/pinctrl/rockchip.h>
78	
79	...
80	
81	pinctrl@20008000 {
82		compatible = "rockchip,rk3066a-pinctrl";
83		rockchip,grf = <&grf>;
84	
85		#address-cells = <1>;
86		#size-cells = <1>;
87		ranges;
88	
89		gpio0: gpio0@20034000 {
90			compatible = "rockchip,gpio-bank";
91			reg = <0x20034000 0x100>;
92			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
93			clocks = <&clk_gates8 9>;
94	
95			gpio-controller;
96			#gpio-cells = <2>;
97	
98			interrupt-controller;
99			#interrupt-cells = <2>;
100		};
101	
102		...
103	
104		pcfg_pull_default: pcfg_pull_default {
105			bias-pull-pin-default
106		};
107	
108		uart2 {
109			uart2_xfer: uart2-xfer {
110				rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
111						<RK_GPIO1 9 1 &pcfg_pull_default>;
112			};
113		};
114	};
115	
116	uart2: serial@20064000 {
117		compatible = "snps,dw-apb-uart";
118		reg = <0x20064000 0x400>;
119		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
120		reg-shift = <2>;
121		reg-io-width = <1>;
122		clocks = <&mux_uart2>;
123		status = "okay";
124	
125		pinctrl-names = "default";
126		pinctrl-0 = <&uart2_xfer>;
127	};
128	
129	Example for rk3188:
130	
131		pinctrl@20008000 {
132			compatible = "rockchip,rk3188-pinctrl";
133			rockchip,grf = <&grf>;
134			rockchip,pmu = <&pmu>;
135			#address-cells = <1>;
136			#size-cells = <1>;
137			ranges;
138	
139			gpio0: gpio0@0x2000a000 {
140				compatible = "rockchip,rk3188-gpio-bank0";
141				reg = <0x2000a000 0x100>;
142				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
143				clocks = <&clk_gates8 9>;
144	
145				gpio-controller;
146				#gpio-cells = <2>;
147	
148				interrupt-controller;
149				#interrupt-cells = <2>;
150			};
151	
152			gpio1: gpio1@0x2003c000 {
153				compatible = "rockchip,gpio-bank";
154				reg = <0x2003c000 0x100>;
155				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
156				clocks = <&clk_gates8 10>;
157	
158				gpio-controller;
159				#gpio-cells = <2>;
160	
161				interrupt-controller;
162				#interrupt-cells = <2>;
163			};
164	
165			...
166	
167		};
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