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Documentation / devicetree / bindings / pinctrl / rockchip,pinctrl.txt




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Based on kernel version 4.8. Page generated on 2016-10-06 23:13 EST.

1	* Rockchip Pinmux Controller
2	
3	The Rockchip Pinmux Controller, enables the IC
4	to share one PAD to several functional blocks. The sharing is done by
5	multiplexing the PAD input/output signals. For each PAD there are several
6	muxing options with option 0 being the use as a GPIO.
7	
8	Please refer to pinctrl-bindings.txt in this directory for details of the
9	common pinctrl bindings used by client devices, including the meaning of the
10	phrase "pin configuration node".
11	
12	The Rockchip pin configuration node is a node of a group of pins which can be
13	used for a specific device or function. This node represents both mux and
14	config of the pins in that group. The 'pins' selects the function mode(also
15	named pin mode) this pin can work on and the 'config' configures various pad
16	settings such as pull-up, etc.
17	
18	The pins are grouped into up to 5 individual pin banks which need to be
19	defined as gpio sub-nodes of the pinmux controller.
20	
21	Required properties for iomux controller:
22	  - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
23			       "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
24			       "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl"
25			       "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl"
26	  - rockchip,grf: phandle referencing a syscon providing the
27		 "general register files"
28	
29	Optional properties for iomux controller:
30	  - rockchip,pmu: phandle referencing a syscon providing the pmu registers
31		 as some SoCs carry parts of the iomux controller registers there.
32		 Required for at least rk3188 and rk3288. On the rk3368 this should
33		 point to the PMUGRF syscon.
34	
35	Deprecated properties for iomux controller:
36	  - reg: first element is the general register space of the iomux controller
37		 It should be large enough to contain also separate pull registers.
38		 second element is the separate pull register space of the rk3188.
39		 Use rockchip,grf and rockchip,pmu described above instead.
40	
41	Required properties for gpio sub nodes:
42	  - compatible: "rockchip,gpio-bank"
43	  - reg: register of the gpio bank (different than the iomux registerset)
44	  - interrupts: base interrupt of the gpio bank in the interrupt controller
45	  - clocks: clock that drives this bank
46	  - gpio-controller: identifies the node as a gpio controller and pin bank.
47	  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
48	    binding is used, the amount of cells must be specified as 2. See generic
49	    GPIO binding documentation for description of particular cells.
50	  - interrupt-controller: identifies the controller node as interrupt-parent.
51	  - #interrupt-cells: the value of this property should be 2 and the interrupt
52	    cells should use the standard two-cell scheme described in
53	    bindings/interrupt-controller/interrupts.txt
54	
55	Deprecated properties for gpio sub nodes:
56	  - compatible: "rockchip,rk3188-gpio-bank0"
57	  - reg: second element: separate pull register for rk3188 bank0, use
58		 rockchip,pmu described above instead
59	
60	Required properties for pin configuration node:
61	  - rockchip,pins: 3 integers array, represents a group of pins mux and config
62	    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
63	    The MUX 0 means gpio and MUX 1 to N mean the specific device function.
64	    The phandle of a node containing the generic pinconfig options
65	    to use, as described in pinctrl-bindings.txt in this directory.
66	
67	Examples:
68	
69	#include <dt-bindings/pinctrl/rockchip.h>
70	
71	...
72	
73	pinctrl@20008000 {
74		compatible = "rockchip,rk3066a-pinctrl";
75		rockchip,grf = <&grf>;
76	
77		#address-cells = <1>;
78		#size-cells = <1>;
79		ranges;
80	
81		gpio0: gpio0@20034000 {
82			compatible = "rockchip,gpio-bank";
83			reg = <0x20034000 0x100>;
84			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
85			clocks = <&clk_gates8 9>;
86	
87			gpio-controller;
88			#gpio-cells = <2>;
89	
90			interrupt-controller;
91			#interrupt-cells = <2>;
92		};
93	
94		...
95	
96		pcfg_pull_default: pcfg_pull_default {
97			bias-pull-pin-default
98		};
99	
100		uart2 {
101			uart2_xfer: uart2-xfer {
102				rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
103						<RK_GPIO1 9 1 &pcfg_pull_default>;
104			};
105		};
106	};
107	
108	uart2: serial@20064000 {
109		compatible = "snps,dw-apb-uart";
110		reg = <0x20064000 0x400>;
111		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
112		reg-shift = <2>;
113		reg-io-width = <1>;
114		clocks = <&mux_uart2>;
115		status = "okay";
116	
117		pinctrl-names = "default";
118		pinctrl-0 = <&uart2_xfer>;
119	};
120	
121	Example for rk3188:
122	
123		pinctrl@20008000 {
124			compatible = "rockchip,rk3188-pinctrl";
125			rockchip,grf = <&grf>;
126			rockchip,pmu = <&pmu>;
127			#address-cells = <1>;
128			#size-cells = <1>;
129			ranges;
130	
131			gpio0: gpio0@0x2000a000 {
132				compatible = "rockchip,rk3188-gpio-bank0";
133				reg = <0x2000a000 0x100>;
134				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
135				clocks = <&clk_gates8 9>;
136	
137				gpio-controller;
138				#gpio-cells = <2>;
139	
140				interrupt-controller;
141				#interrupt-cells = <2>;
142			};
143	
144			gpio1: gpio1@0x2003c000 {
145				compatible = "rockchip,gpio-bank";
146				reg = <0x2003c000 0x100>;
147				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
148				clocks = <&clk_gates8 10>;
149	
150				gpio-controller;
151				#gpio-cells = <2>;
152	
153				interrupt-controller;
154				#interrupt-cells = <2>;
155			};
156	
157			...
158	
159		};
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