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Based on kernel version 4.13.3. Page generated on 2017-09-23 13:56 EST.

1	Overview of Linux kernel SPI support
2	====================================
3	
4	02-Feb-2012
5	
6	What is SPI?
7	------------
8	The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
9	link used to connect microcontrollers to sensors, memory, and peripherals.
10	It's a simple "de facto" standard, not complicated enough to acquire a
11	standardization body.  SPI uses a master/slave configuration.
12	
13	The three signal wires hold a clock (SCK, often on the order of 10 MHz),
14	and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
15	Slave Out" (MISO) signals.  (Other names are also used.)  There are four
16	clocking modes through which data is exchanged; mode-0 and mode-3 are most
17	commonly used.  Each clock cycle shifts data out and data in; the clock
18	doesn't cycle except when there is a data bit to shift.  Not all data bits
19	are used though; not every protocol uses those full duplex capabilities.
20	
21	SPI masters use a fourth "chip select" line to activate a given SPI slave
22	device, so those three signal wires may be connected to several chips
23	in parallel.  All SPI slaves support chipselects; they are usually active
24	low signals, labeled nCSx for slave 'x' (e.g. nCS0).  Some devices have
25	other signals, often including an interrupt to the master.
26	
27	Unlike serial busses like USB or SMBus, even low level protocols for
28	SPI slave functions are usually not interoperable between vendors
29	(except for commodities like SPI memory chips).
30	
31	  - SPI may be used for request/response style device protocols, as with
32	    touchscreen sensors and memory chips.
33	
34	  - It may also be used to stream data in either direction (half duplex),
35	    or both of them at the same time (full duplex).
36	
37	  - Some devices may use eight bit words.  Others may use different word
38	    lengths, such as streams of 12-bit or 20-bit digital samples.
39	
40	  - Words are usually sent with their most significant bit (MSB) first,
41	    but sometimes the least significant bit (LSB) goes first instead.
42	
43	  - Sometimes SPI is used to daisy-chain devices, like shift registers.
44	
45	In the same way, SPI slaves will only rarely support any kind of automatic
46	discovery/enumeration protocol.  The tree of slave devices accessible from
47	a given SPI master will normally be set up manually, with configuration
48	tables.
49	
50	SPI is only one of the names used by such four-wire protocols, and
51	most controllers have no problem handling "MicroWire" (think of it as
52	half-duplex SPI, for request/response protocols), SSP ("Synchronous
53	Serial Protocol"), PSP ("Programmable Serial Protocol"), and other
54	related protocols.
55	
56	Some chips eliminate a signal line by combining MOSI and MISO, and
57	limiting themselves to half-duplex at the hardware level.  In fact
58	some SPI chips have this signal mode as a strapping option.  These
59	can be accessed using the same programming interface as SPI, but of
60	course they won't handle full duplex transfers.  You may find such
61	chips described as using "three wire" signaling: SCK, data, nCSx.
62	(That data line is sometimes called MOMI or SISO.)
63	
64	Microcontrollers often support both master and slave sides of the SPI
65	protocol.  This document (and Linux) supports both the master and slave
66	sides of SPI interactions.
67	
68	
69	Who uses it?  On what kinds of systems?
70	---------------------------------------
71	Linux developers using SPI are probably writing device drivers for embedded
72	systems boards.  SPI is used to control external chips, and it is also a
73	protocol supported by every MMC or SD memory card.  (The older "DataFlash"
74	cards, predating MMC cards but using the same connectors and card shape,
75	support only SPI.)  Some PC hardware uses SPI flash for BIOS code.
76	
77	SPI slave chips range from digital/analog converters used for analog
78	sensors and codecs, to memory, to peripherals like USB controllers
79	or Ethernet adapters; and more.
80	
81	Most systems using SPI will integrate a few devices on a mainboard.
82	Some provide SPI links on expansion connectors; in cases where no
83	dedicated SPI controller exists, GPIO pins can be used to create a
84	low speed "bitbanging" adapter.  Very few systems will "hotplug" an SPI
85	controller; the reasons to use SPI focus on low cost and simple operation,
86	and if dynamic reconfiguration is important, USB will often be a more
87	appropriate low-pincount peripheral bus.
88	
89	Many microcontrollers that can run Linux integrate one or more I/O
90	interfaces with SPI modes.  Given SPI support, they could use MMC or SD
91	cards without needing a special purpose MMC/SD/SDIO controller.
92	
93	
94	I'm confused.  What are these four SPI "clock modes"?
95	-----------------------------------------------------
96	It's easy to be confused here, and the vendor documentation you'll
97	find isn't necessarily helpful.  The four modes combine two mode bits:
98	
99	 - CPOL indicates the initial clock polarity.  CPOL=0 means the
100	   clock starts low, so the first (leading) edge is rising, and
101	   the second (trailing) edge is falling.  CPOL=1 means the clock
102	   starts high, so the first (leading) edge is falling.
103	
104	 - CPHA indicates the clock phase used to sample data; CPHA=0 says
105	   sample on the leading edge, CPHA=1 means the trailing edge.
106	
107	   Since the signal needs to stablize before it's sampled, CPHA=0
108	   implies that its data is written half a clock before the first
109	   clock edge.  The chipselect may have made it become available.
110	
111	Chip specs won't always say "uses SPI mode X" in as many words,
112	but their timing diagrams will make the CPOL and CPHA modes clear.
113	
114	In the SPI mode number, CPOL is the high order bit and CPHA is the
115	low order bit.  So when a chip's timing diagram shows the clock
116	starting low (CPOL=0) and data stabilized for sampling during the
117	trailing clock edge (CPHA=1), that's SPI mode 1.
118	
119	Note that the clock mode is relevant as soon as the chipselect goes
120	active.  So the master must set the clock to inactive before selecting
121	a slave, and the slave can tell the chosen polarity by sampling the
122	clock level when its select line goes active.  That's why many devices
123	support for example both modes 0 and 3:  they don't care about polarity,
124	and always clock data in/out on rising clock edges.
125	
126	
127	How do these driver programming interfaces work?
128	------------------------------------------------
129	The <linux/spi/spi.h> header file includes kerneldoc, as does the
130	main source code, and you should certainly read that chapter of the
131	kernel API document.  This is just an overview, so you get the big
132	picture before those details.
133	
134	SPI requests always go into I/O queues.  Requests for a given SPI device
135	are always executed in FIFO order, and complete asynchronously through
136	completion callbacks.  There are also some simple synchronous wrappers
137	for those calls, including ones for common transaction types like writing
138	a command and then reading its response.
139	
140	There are two types of SPI driver, here called:
141	
142	  Controller drivers ... controllers may be built into System-On-Chip
143		processors, and often support both Master and Slave roles.
144		These drivers touch hardware registers and may use DMA.
145		Or they can be PIO bitbangers, needing just GPIO pins.
146	
147	  Protocol drivers ... these pass messages through the controller
148		driver to communicate with a Slave or Master device on the
149		other side of an SPI link.
150	
151	So for example one protocol driver might talk to the MTD layer to export
152	data to filesystems stored on SPI flash like DataFlash; and others might
153	control audio interfaces, present touchscreen sensors as input interfaces,
154	or monitor temperature and voltage levels during industrial processing.
155	And those might all be sharing the same controller driver.
156	
157	A "struct spi_device" encapsulates the controller-side interface between
158	those two types of drivers.
159	
160	There is a minimal core of SPI programming interfaces, focussing on
161	using the driver model to connect controller and protocol drivers using
162	device tables provided by board specific initialization code.  SPI
163	shows up in sysfs in several locations:
164	
165	   /sys/devices/.../CTLR ... physical node for a given SPI controller
166	
167	   /sys/devices/.../CTLR/spiB.C ... spi_device on bus "B",
168		chipselect C, accessed through CTLR.
169	
170	   /sys/bus/spi/devices/spiB.C ... symlink to that physical
171	   	.../CTLR/spiB.C device
172	
173	   /sys/devices/.../CTLR/spiB.C/modalias ... identifies the driver
174		that should be used with this device (for hotplug/coldplug)
175	
176	   /sys/bus/spi/drivers/D ... driver for one or more spi*.* devices
177	
178	   /sys/class/spi_master/spiB ... symlink (or actual device node) to
179		a logical node which could hold class related state for the SPI
180		master controller managing bus "B".  All spiB.* devices share one
181		physical SPI bus segment, with SCLK, MOSI, and MISO.
182	
183	   /sys/devices/.../CTLR/slave ... virtual file for (un)registering the
184		slave device for an SPI slave controller.
185		Writing the driver name of an SPI slave handler to this file
186		registers the slave device; writing "(null)" unregisters the slave
187		device.
188		Reading from this file shows the name of the slave device ("(null)"
189		if not registered).
190	
191	   /sys/class/spi_slave/spiB ... symlink (or actual device node) to
192		a logical node which could hold class related state for the SPI
193		slave controller on bus "B".  When registered, a single spiB.*
194		device is present here, possible sharing the physical SPI bus
195		segment with other SPI slave devices.
196	
197	Note that the actual location of the controller's class state depends
198	on whether you enabled CONFIG_SYSFS_DEPRECATED or not.  At this time,
199	the only class-specific state is the bus number ("B" in "spiB"), so
200	those /sys/class entries are only useful to quickly identify busses.
201	
202	
203	How does board-specific init code declare SPI devices?
204	------------------------------------------------------
205	Linux needs several kinds of information to properly configure SPI devices.
206	That information is normally provided by board-specific code, even for
207	chips that do support some of automated discovery/enumeration.
208	
209	DECLARE CONTROLLERS
210	
211	The first kind of information is a list of what SPI controllers exist.
212	For System-on-Chip (SOC) based boards, these will usually be platform
213	devices, and the controller may need some platform_data in order to
214	operate properly.  The "struct platform_device" will include resources
215	like the physical address of the controller's first register and its IRQ.
216	
217	Platforms will often abstract the "register SPI controller" operation,
218	maybe coupling it with code to initialize pin configurations, so that
219	the arch/.../mach-*/board-*.c files for several boards can all share the
220	same basic controller setup code.  This is because most SOCs have several
221	SPI-capable controllers, and only the ones actually usable on a given
222	board should normally be set up and registered.
223	
224	So for example arch/.../mach-*/board-*.c files might have code like:
225	
226		#include <mach/spi.h>	/* for mysoc_spi_data */
227	
228		/* if your mach-* infrastructure doesn't support kernels that can
229		 * run on multiple boards, pdata wouldn't benefit from "__init".
230		 */
231		static struct mysoc_spi_data pdata __initdata = { ... };
232	
233		static __init board_init(void)
234		{
235			...
236			/* this board only uses SPI controller #2 */
237			mysoc_register_spi(2, &pdata);
238			...
239		}
240	
241	And SOC-specific utility code might look something like:
242	
243		#include <mach/spi.h>
244	
245		static struct platform_device spi2 = { ... };
246	
247		void mysoc_register_spi(unsigned n, struct mysoc_spi_data *pdata)
248		{
249			struct mysoc_spi_data *pdata2;
250	
251			pdata2 = kmalloc(sizeof *pdata2, GFP_KERNEL);
252			*pdata2 = pdata;
253			...
254			if (n == 2) {
255				spi2->dev.platform_data = pdata2;
256				register_platform_device(&spi2);
257	
258				/* also: set up pin modes so the spi2 signals are
259				 * visible on the relevant pins ... bootloaders on
260				 * production boards may already have done this, but
261				 * developer boards will often need Linux to do it.
262				 */
263			}
264			...
265		}
266	
267	Notice how the platform_data for boards may be different, even if the
268	same SOC controller is used.  For example, on one board SPI might use
269	an external clock, where another derives the SPI clock from current
270	settings of some master clock.
271	
272	
273	DECLARE SLAVE DEVICES
274	
275	The second kind of information is a list of what SPI slave devices exist
276	on the target board, often with some board-specific data needed for the
277	driver to work correctly.
278	
279	Normally your arch/.../mach-*/board-*.c files would provide a small table
280	listing the SPI devices on each board.  (This would typically be only a
281	small handful.)  That might look like:
282	
283		static struct ads7846_platform_data ads_info = {
284			.vref_delay_usecs	= 100,
285			.x_plate_ohms		= 580,
286			.y_plate_ohms		= 410,
287		};
288	
289		static struct spi_board_info spi_board_info[] __initdata = {
290		{
291			.modalias	= "ads7846",
292			.platform_data	= &ads_info,
293			.mode		= SPI_MODE_0,
294			.irq		= GPIO_IRQ(31),
295			.max_speed_hz	= 120000 /* max sample rate at 3V */ * 16,
296			.bus_num	= 1,
297			.chip_select	= 0,
298		},
299		};
300	
301	Again, notice how board-specific information is provided; each chip may need
302	several types.  This example shows generic constraints like the fastest SPI
303	clock to allow (a function of board voltage in this case) or how an IRQ pin
304	is wired, plus chip-specific constraints like an important delay that's
305	changed by the capacitance at one pin.
306	
307	(There's also "controller_data", information that may be useful to the
308	controller driver.  An example would be peripheral-specific DMA tuning
309	data or chipselect callbacks.  This is stored in spi_device later.)
310	
311	The board_info should provide enough information to let the system work
312	without the chip's driver being loaded.  The most troublesome aspect of
313	that is likely the SPI_CS_HIGH bit in the spi_device.mode field, since
314	sharing a bus with a device that interprets chipselect "backwards" is
315	not possible until the infrastructure knows how to deselect it.
316	
317	Then your board initialization code would register that table with the SPI
318	infrastructure, so that it's available later when the SPI master controller
319	driver is registered:
320	
321		spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
322	
323	Like with other static board-specific setup, you won't unregister those.
324	
325	The widely used "card" style computers bundle memory, cpu, and little else
326	onto a card that's maybe just thirty square centimeters.  On such systems,
327	your arch/.../mach-.../board-*.c file would primarily provide information
328	about the devices on the mainboard into which such a card is plugged.  That
329	certainly includes SPI devices hooked up through the card connectors!
330	
331	
332	NON-STATIC CONFIGURATIONS
333	
334	Developer boards often play by different rules than product boards, and one
335	example is the potential need to hotplug SPI devices and/or controllers.
336	
337	For those cases you might need to use spi_busnum_to_master() to look
338	up the spi bus master, and will likely need spi_new_device() to provide the
339	board info based on the board that was hotplugged.  Of course, you'd later
340	call at least spi_unregister_device() when that board is removed.
341	
342	When Linux includes support for MMC/SD/SDIO/DataFlash cards through SPI, those
343	configurations will also be dynamic.  Fortunately, such devices all support
344	basic device identification probes, so they should hotplug normally.
345	
346	
347	How do I write an "SPI Protocol Driver"?
348	----------------------------------------
349	Most SPI drivers are currently kernel drivers, but there's also support
350	for userspace drivers.  Here we talk only about kernel drivers.
351	
352	SPI protocol drivers somewhat resemble platform device drivers:
353	
354		static struct spi_driver CHIP_driver = {
355			.driver = {
356				.name		= "CHIP",
357				.owner		= THIS_MODULE,
358				.pm		= &CHIP_pm_ops,
359			},
360	
361			.probe		= CHIP_probe,
362			.remove		= CHIP_remove,
363		};
364	
365	The driver core will automatically attempt to bind this driver to any SPI
366	device whose board_info gave a modalias of "CHIP".  Your probe() code
367	might look like this unless you're creating a device which is managing
368	a bus (appearing under /sys/class/spi_master).
369	
370		static int CHIP_probe(struct spi_device *spi)
371		{
372			struct CHIP			*chip;
373			struct CHIP_platform_data	*pdata;
374	
375			/* assuming the driver requires board-specific data: */
376			pdata = &spi->dev.platform_data;
377			if (!pdata)
378				return -ENODEV;
379	
380			/* get memory for driver's per-chip state */
381			chip = kzalloc(sizeof *chip, GFP_KERNEL);
382			if (!chip)
383				return -ENOMEM;
384			spi_set_drvdata(spi, chip);
385	
386			... etc
387			return 0;
388		}
389	
390	As soon as it enters probe(), the driver may issue I/O requests to
391	the SPI device using "struct spi_message".  When remove() returns,
392	or after probe() fails, the driver guarantees that it won't submit
393	any more such messages.
394	
395	  - An spi_message is a sequence of protocol operations, executed
396	    as one atomic sequence.  SPI driver controls include:
397	
398	      + when bidirectional reads and writes start ... by how its
399	        sequence of spi_transfer requests is arranged;
400	
401	      + which I/O buffers are used ... each spi_transfer wraps a
402	        buffer for each transfer direction, supporting full duplex
403	        (two pointers, maybe the same one in both cases) and half
404	        duplex (one pointer is NULL) transfers;
405	
406	      + optionally defining short delays after transfers ... using
407	        the spi_transfer.delay_usecs setting (this delay can be the
408	        only protocol effect, if the buffer length is zero);
409	
410	      + whether the chipselect becomes inactive after a transfer and
411	        any delay ... by using the spi_transfer.cs_change flag;
412	
413	      + hinting whether the next message is likely to go to this same
414	        device ... using the spi_transfer.cs_change flag on the last
415		transfer in that atomic group, and potentially saving costs
416		for chip deselect and select operations.
417	
418	  - Follow standard kernel rules, and provide DMA-safe buffers in
419	    your messages.  That way controller drivers using DMA aren't forced
420	    to make extra copies unless the hardware requires it (e.g. working
421	    around hardware errata that force the use of bounce buffering).
422	
423	    If standard dma_map_single() handling of these buffers is inappropriate,
424	    you can use spi_message.is_dma_mapped to tell the controller driver
425	    that you've already provided the relevant DMA addresses.
426	
427	  - The basic I/O primitive is spi_async().  Async requests may be
428	    issued in any context (irq handler, task, etc) and completion
429	    is reported using a callback provided with the message.
430	    After any detected error, the chip is deselected and processing
431	    of that spi_message is aborted.
432	
433	  - There are also synchronous wrappers like spi_sync(), and wrappers
434	    like spi_read(), spi_write(), and spi_write_then_read().  These
435	    may be issued only in contexts that may sleep, and they're all
436	    clean (and small, and "optional") layers over spi_async().
437	
438	  - The spi_write_then_read() call, and convenience wrappers around
439	    it, should only be used with small amounts of data where the
440	    cost of an extra copy may be ignored.  It's designed to support
441	    common RPC-style requests, such as writing an eight bit command
442	    and reading a sixteen bit response -- spi_w8r16() being one its
443	    wrappers, doing exactly that.
444	
445	Some drivers may need to modify spi_device characteristics like the
446	transfer mode, wordsize, or clock rate.  This is done with spi_setup(),
447	which would normally be called from probe() before the first I/O is
448	done to the device.  However, that can also be called at any time
449	that no message is pending for that device.
450	
451	While "spi_device" would be the bottom boundary of the driver, the
452	upper boundaries might include sysfs (especially for sensor readings),
453	the input layer, ALSA, networking, MTD, the character device framework,
454	or other Linux subsystems.
455	
456	Note that there are two types of memory your driver must manage as part
457	of interacting with SPI devices.
458	
459	  - I/O buffers use the usual Linux rules, and must be DMA-safe.
460	    You'd normally allocate them from the heap or free page pool.
461	    Don't use the stack, or anything that's declared "static".
462	
463	  - The spi_message and spi_transfer metadata used to glue those
464	    I/O buffers into a group of protocol transactions.  These can
465	    be allocated anywhere it's convenient, including as part of
466	    other allocate-once driver data structures.  Zero-init these.
467	
468	If you like, spi_message_alloc() and spi_message_free() convenience
469	routines are available to allocate and zero-initialize an spi_message
470	with several transfers.
471	
472	
473	How do I write an "SPI Master Controller Driver"?
474	-------------------------------------------------
475	An SPI controller will probably be registered on the platform_bus; write
476	a driver to bind to the device, whichever bus is involved.
477	
478	The main task of this type of driver is to provide an "spi_master".
479	Use spi_alloc_master() to allocate the master, and spi_master_get_devdata()
480	to get the driver-private data allocated for that device.
481	
482		struct spi_master	*master;
483		struct CONTROLLER	*c;
484	
485		master = spi_alloc_master(dev, sizeof *c);
486		if (!master)
487			return -ENODEV;
488	
489		c = spi_master_get_devdata(master);
490	
491	The driver will initialize the fields of that spi_master, including the
492	bus number (maybe the same as the platform device ID) and three methods
493	used to interact with the SPI core and SPI protocol drivers.  It will
494	also initialize its own internal state.  (See below about bus numbering
495	and those methods.)
496	
497	After you initialize the spi_master, then use spi_register_master() to
498	publish it to the rest of the system. At that time, device nodes for the
499	controller and any predeclared spi devices will be made available, and
500	the driver model core will take care of binding them to drivers.
501	
502	If you need to remove your SPI controller driver, spi_unregister_master()
503	will reverse the effect of spi_register_master().
504	
505	
506	BUS NUMBERING
507	
508	Bus numbering is important, since that's how Linux identifies a given
509	SPI bus (shared SCK, MOSI, MISO).  Valid bus numbers start at zero.  On
510	SOC systems, the bus numbers should match the numbers defined by the chip
511	manufacturer.  For example, hardware controller SPI2 would be bus number 2,
512	and spi_board_info for devices connected to it would use that number.
513	
514	If you don't have such hardware-assigned bus number, and for some reason
515	you can't just assign them, then provide a negative bus number.  That will
516	then be replaced by a dynamically assigned number. You'd then need to treat
517	this as a non-static configuration (see above).
518	
519	
520	SPI MASTER METHODS
521	
522	    master->setup(struct spi_device *spi)
523		This sets up the device clock rate, SPI mode, and word sizes.
524		Drivers may change the defaults provided by board_info, and then
525		call spi_setup(spi) to invoke this routine.  It may sleep.
526	
527		Unless each SPI slave has its own configuration registers, don't
528		change them right away ... otherwise drivers could corrupt I/O
529		that's in progress for other SPI devices.
530	
531			** BUG ALERT:  for some reason the first version of
532			** many spi_master drivers seems to get this wrong.
533			** When you code setup(), ASSUME that the controller
534			** is actively processing transfers for another device.
535	
536	    master->cleanup(struct spi_device *spi)
537		Your controller driver may use spi_device.controller_state to hold
538		state it dynamically associates with that device.  If you do that,
539		be sure to provide the cleanup() method to free that state.
540	
541	    master->prepare_transfer_hardware(struct spi_master *master)
542		This will be called by the queue mechanism to signal to the driver
543		that a message is coming in soon, so the subsystem requests the
544		driver to prepare the transfer hardware by issuing this call.
545		This may sleep.
546	
547	    master->unprepare_transfer_hardware(struct spi_master *master)
548		This will be called by the queue mechanism to signal to the driver
549		that there are no more messages pending in the queue and it may
550		relax the hardware (e.g. by power management calls). This may sleep.
551	
552	    master->transfer_one_message(struct spi_master *master,
553					 struct spi_message *mesg)
554		The subsystem calls the driver to transfer a single message while
555		queuing transfers that arrive in the meantime. When the driver is
556		finished with this message, it must call
557		spi_finalize_current_message() so the subsystem can issue the next
558		message. This may sleep.
559	
560	    master->transfer_one(struct spi_master *master, struct spi_device *spi,
561				 struct spi_transfer *transfer)
562		The subsystem calls the driver to transfer a single transfer while
563		queuing transfers that arrive in the meantime. When the driver is
564		finished with this transfer, it must call
565		spi_finalize_current_transfer() so the subsystem can issue the next
566		transfer. This may sleep. Note: transfer_one and transfer_one_message
567		are mutually exclusive; when both are set, the generic subsystem does
568		not call your transfer_one callback.
569	
570		Return values:
571		negative errno: error
572		0: transfer is finished
573		1: transfer is still in progress
574	
575	    DEPRECATED METHODS
576	
577	    master->transfer(struct spi_device *spi, struct spi_message *message)
578		This must not sleep. Its responsibility is to arrange that the
579		transfer happens and its complete() callback is issued. The two
580		will normally happen later, after other transfers complete, and
581		if the controller is idle it will need to be kickstarted. This
582		method is not used on queued controllers and must be NULL if
583		transfer_one_message() and (un)prepare_transfer_hardware() are
584		implemented.
585	
586	
587	SPI MESSAGE QUEUE
588	
589	If you are happy with the standard queueing mechanism provided by the
590	SPI subsystem, just implement the queued methods specified above. Using
591	the message queue has the upside of centralizing a lot of code and
592	providing pure process-context execution of methods. The message queue
593	can also be elevated to realtime priority on high-priority SPI traffic.
594	
595	Unless the queueing mechanism in the SPI subsystem is selected, the bulk
596	of the driver will be managing the I/O queue fed by the now deprecated
597	function transfer().
598	
599	That queue could be purely conceptual.  For example, a driver used only
600	for low-frequency sensor access might be fine using synchronous PIO.
601	
602	But the queue will probably be very real, using message->queue, PIO,
603	often DMA (especially if the root filesystem is in SPI flash), and
604	execution contexts like IRQ handlers, tasklets, or workqueues (such
605	as keventd).  Your driver can be as fancy, or as simple, as you need.
606	Such a transfer() method would normally just add the message to a
607	queue, and then start some asynchronous transfer engine (unless it's
608	already running).
609	
610	
611	THANKS TO
612	---------
613	Contributors to Linux-SPI discussions include (in alphabetical order,
614	by last name):
615	
616	Mark Brown
617	David Brownell
618	Russell King
619	Grant Likely
620	Dmitry Pervushin
621	Stephen Street
622	Mark Underwood
623	Andrew Victor
624	Linus Walleij
625	Vitaly Wool
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