About Kernel Documentation Linux Kernel Contact Linux Resources Linux Blog

Documentation / devicetree / bindings / c6x / interrupt.txt




Custom Search

Based on kernel version 3.15.4. Page generated on 2014-07-07 09:00 EST.

1	C6X Interrupt Chips
2	-------------------
3	
4	* C64X+ Core Interrupt Controller
5	
6	  The core interrupt controller provides 16 prioritized interrupts to the
7	  C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
8	  Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
9	  sources coming from outside the core.
10	
11	  Required properties:
12	  --------------------
13	  - compatible: Should be "ti,c64x+core-pic";
14	  - #interrupt-cells: <1>
15	
16	  Interrupt Specifier Definition
17	  ------------------------------
18	  Single cell specifying the core interrupt priority level (4-15) where
19	  4 is highest priority and 15 is lowest priority.
20	
21	  Example
22	  -------
23	  core_pic: interrupt-controller@0 {
24		interrupt-controller;
25		#interrupt-cells = <1>;
26		compatible = "ti,c64x+core-pic";
27	  };
28	
29	
30	
31	* C64x+ Megamodule Interrupt Controller
32	
33	  The megamodule PIC consists of four interrupt mupliplexers each of which
34	  combine up to 32 interrupt inputs into a single interrupt output which
35	  may be cascaded into the core interrupt controller. The megamodule PIC
36	  has a total of 12 outputs cascading into the core interrupt controller.
37	  One for each core interrupt priority level. In addition to the combined
38	  interrupt sources, individual megamodule interrupts may be cascaded to
39	  the core interrupt controller. When an individual interrupt is cascaded,
40	  it is no longer handled through a megamodule interrupt combiner and is
41	  considered to have the core interrupt controller as the parent.
42	
43	  Required properties:
44	  --------------------
45	  - compatible: "ti,c64x+megamod-pic"
46	  - interrupt-controller
47	  - #interrupt-cells: <1>
48	  - reg: base address and size of register area
49	  - interrupt-parent: must be core interrupt controller
50	  - interrupts: This should have four cells; one for each interrupt combiner.
51	                The cells contain the core priority interrupt to which the
52	                corresponding combiner output is wired.
53	
54	  Optional properties:
55	  --------------------
56	  - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
57	                             priority interrupts. The first cell corresponds to
58	                             core priority 4 and the last cell corresponds to
59	                             core priority 15. The value of each cell is the
60	                             megamodule interrupt source which is MUXed to
61	                             the core interrupt corresponding to the cell
62	                             position. Allowed values are 4 - 127. Mapping for
63	                             interrupts 0 - 3 (combined interrupt sources) are
64	                             ignored.
65	
66	  Interrupt Specifier Definition
67	  ------------------------------
68	  Single cell specifying the megamodule interrupt source (4-127). Note that
69	  interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
70	  use the core interrupt controller as their parent and the specifier will
71	  be the core priority level, not the megamodule interrupt number.
72	
73	  Examples
74	  --------
75	  megamod_pic: interrupt-controller@1800000 {
76		compatible = "ti,c64x+megamod-pic";
77		interrupt-controller;
78		#interrupt-cells = <1>;
79		reg = <0x1800000 0x1000>;
80		interrupt-parent = <&core_pic>;
81		interrupts = < 12 13 14 15 >;
82	  };
83	
84	  This is a minimal example where all individual interrupts go through a
85	  combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
86	  to interrupt 13, etc.
87	
88	
89	  megamod_pic: interrupt-controller@1800000 {
90		compatible = "ti,c64x+megamod-pic";
91		interrupt-controller;
92		#interrupt-cells = <1>;
93		reg = <0x1800000 0x1000>;
94		interrupt-parent = <&core_pic>;
95		interrupts = < 12 13 14 15 >;
96		ti,c64x+megamod-pic-mux = <  0  0  0  0
97	                                    32  0  0  0
98	                                     0  0  0  0 >;
99	  };
100	
101	  This the same as the first example except that megamodule interrupt 32 is
102	  mapped directly to core priority interrupt 8. The node using this interrupt
103	  must set the core controller as its interrupt parent and use 8 in the
104	  interrupt specifier value.
Hide Line Numbers
About Kernel Documentation Linux Kernel Contact Linux Resources Linux Blog

Information is copyright its respective author. All material is available from the Linux Kernel Source distributed under a GPL License. This page is provided as a free service by mjmwired.net.