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Documentation / devicetree / bindings / timer / nvidia,tegra20-timer.txt




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Based on kernel version 3.9. Page generated on 2013-05-02 23:02 EST.

1	NVIDIA Tegra20 timer
2	
3	The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
4	running counter. The first two channels may also trigger a watchdog reset.
5	
6	Required properties:
7	
8	- compatible : should be "nvidia,tegra20-timer".
9	- reg : Specifies base physical address and size of the registers.
10	- interrupts : A list of 4 interrupts; one per timer channel.
11	
12	Example:
13	
14	timer {
15		compatible = "nvidia,tegra20-timer";
16		reg = <0x60005000 0x60>;
17		interrupts = <0 0 0x04
18				0 1 0x04
19				0 41 0x04
20				0 42 0x04>;
21	};
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