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Documentation / devicetree / bindings / timer / nvidia,tegra30-timer.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:02 EST.

1	NVIDIA Tegra30 timer
2	
3	The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
4	running counter, and 5 watchdog modules. The first two channels may also
5	trigger a legacy watchdog reset.
6	
7	Required properties:
8	
9	- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
10	- reg : Specifies base physical address and size of the registers.
11	- interrupts : A list of 6 interrupts; one per each of timer channels 1
12	    through 5, and one for the shared interrupt for the remaining channels.
13	
14	timer {
15		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
16		reg = <0x60005000 0x400>;
17		interrupts = <0 0 0x04
18			      0 1 0x04
19			      0 41 0x04
20			      0 42 0x04
21			      0 121 0x04
22			      0 122 0x04>;
23	};
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