Based on kernel version 3.13. Page generated on 2014-01-20 22:03 EST.
1 This document describes the i2c protocol. Or will, when it is finished :-) 2 3 Key to symbols 4 ============== 5 6 S (1 bit) : Start bit 7 P (1 bit) : Stop bit 8 Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0. 9 A, NA (1 bit) : Accept and reverse accept bit. 10 Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to 11 get a 10 bit I2C address. 12 Comm (8 bits): Command byte, a data byte which often selects a register on 13 the device. 14 Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh 15 for 16 bit data. 16 Count (8 bits): A data byte containing the length of a block operation. 17 18 [..]: Data sent by I2C device, as opposed to data sent by the host adapter. 19 20 21 Simple send transaction 22 ====================== 23 24 This corresponds to i2c_master_send. 25 26 S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P 27 28 29 Simple receive transaction 30 =========================== 31 32 This corresponds to i2c_master_recv 33 34 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P 35 36 37 Combined transactions 38 ==================== 39 40 This corresponds to i2c_transfer 41 42 They are just like the above transactions, but instead of a stop bit P 43 a start bit S is sent and the transaction continues. An example of 44 a byte read, followed by a byte write: 45 46 S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P 47 48 49 Modified transactions 50 ===================== 51 52 The following modifications to the I2C protocol can also be generated, 53 with the exception of I2C_M_NOSTART these are usually only needed to 54 work around device issues: 55 56 Flag I2C_M_NOSTART: 57 In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some 58 point. For example, setting I2C_M_NOSTART on the second partial message 59 generates something like: 60 S Addr Rd [A] [Data] NA Data [A] P 61 If you set the I2C_M_NOSTART variable for the first partial message, 62 we do not generate Addr, but we do generate the startbit S. This will 63 probably confuse all other clients on your bus, so don't try this. 64 65 This is often used to gather transmits from multiple data buffers in 66 system memory into something that appears as a single transfer to the 67 I2C device but may also be used between direction changes by some 68 rare devices. 69 70 Flags I2C_M_REV_DIR_ADDR 71 This toggles the Rd/Wr flag. That is, if you want to do a write, but 72 need to emit an Rd instead of a Wr, or vice versa, you set this 73 flag. For example: 74 S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P 75 76 Flags I2C_M_IGNORE_NAK 77 Normally message is interrupted immediately if there is [NA] from the 78 client. Setting this flag treats any [NA] as [A], and all of 79 message is sent. 80 These messages may still fail to SCL lo->hi timeout. 81 82 Flags I2C_M_NO_RD_ACK 83 In a read message, master A/NA bit is skipped.