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Documentation / i2c / smbus-protocol

Based on kernel version 2.6.26. Page generated on 2008-07-16 21:12 EST.

1	SMBus Protocol Summary
2	======================
3	The following is a summary of the SMBus protocol. It applies to
4	all revisions of the protocol (1.0, 1.1, and 2.0).
5	Certain protocol features which are not supported by
6	this package are briefly described at the end of this document.
7	
8	Some adapters understand only the SMBus (System Management Bus) protocol,
9	which is a subset from the I2C protocol. Fortunately, many devices use
10	only the same subset, which makes it possible to put them on an SMBus.
11	If you write a driver for some I2C device, please try to use the SMBus
12	commands if at all possible (if the device uses only that subset of the
13	I2C protocol). This makes it possible to use the device driver on both
14	SMBus adapters and I2C adapters (the SMBus command set is automatically
15	translated to I2C on I2C adapters, but plain I2C commands can not be
16	handled at all on most pure SMBus adapters).
17	
18	Below is a list of SMBus commands.
19	
20	Key to symbols
21	==============
22	
23	S     (1 bit) : Start bit
24	P     (1 bit) : Stop bit
25	Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
26	A, NA (1 bit) : Accept and reverse accept bit. 
27	Addr  (7 bits): I2C 7 bit address. Note that this can be expanded as usual to 
28	                get a 10 bit I2C address.
29	Comm  (8 bits): Command byte, a data byte which often selects a register on
30	                the device.
31	Data  (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
32	                for 16 bit data.
33	Count (8 bits): A data byte containing the length of a block operation.
34	
35	[..]: Data sent by I2C device, as opposed to data sent by the host adapter.
36	
37	
38	SMBus Write Quick
39	=================
40	
41	This sends a single bit to the device, at the place of the Rd/Wr bit.
42	There is no equivalent Read Quick command.
43	
44	A Addr Rd/Wr [A] P
45	
46	
47	SMBus Read Byte
48	===============
49	
50	This reads a single byte from a device, without specifying a device
51	register. Some devices are so simple that this interface is enough; for
52	others, it is a shorthand if you want to read the same register as in
53	the previous SMBus command.
54	
55	S Addr Rd [A] [Data] NA P
56	
57	
58	SMBus Write Byte
59	================
60	
61	This is the reverse of Read Byte: it sends a single byte to a device.
62	See Read Byte for more information.
63	
64	S Addr Wr [A] Data [A] P
65	
66	
67	SMBus Read Byte Data
68	====================
69	
70	This reads a single byte from a device, from a designated register.
71	The register is specified through the Comm byte.
72	
73	S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P
74	
75	
76	SMBus Read Word Data
77	====================
78	
79	This command is very like Read Byte Data; again, data is read from a
80	device, from a designated register that is specified through the Comm
81	byte. But this time, the data is a complete word (16 bits).
82	
83	S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
84	
85	
86	SMBus Write Byte Data
87	=====================
88	
89	This writes a single byte to a device, to a designated register. The
90	register is specified through the Comm byte. This is the opposite of
91	the Read Byte Data command.
92	
93	S Addr Wr [A] Comm [A] Data [A] P
94	
95	
96	SMBus Write Word Data
97	=====================
98	
99	This is the opposite operation of the Read Word Data command. 16 bits
100	of data is written to a device, to the designated register that is
101	specified through the Comm byte. 
102	
103	S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
104	
105	
106	SMBus Process Call
107	==================
108	
109	This command selects a device register (through the Comm byte), sends
110	16 bits of data to it, and reads 16 bits of data in return.
111	
112	S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] 
113	                             S Addr Rd [A] [DataLow] A [DataHigh] NA P
114	
115	
116	SMBus Block Read
117	================
118	
119	This command reads a block of up to 32 bytes from a device, from a 
120	designated register that is specified through the Comm byte. The amount
121	of data is specified by the device in the Count byte.
122	
123	S Addr Wr [A] Comm [A] 
124	           S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
125	
126	
127	SMBus Block Write
128	=================
129	
130	The opposite of the Block Read command, this writes up to 32 bytes to 
131	a device, to a designated register that is specified through the
132	Comm byte. The amount of data is specified in the Count byte.
133	
134	S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
135	
136	
137	SMBus Block Process Call
138	========================
139	
140	SMBus Block Process Call was introduced in Revision 2.0 of the specification.
141	
142	This command selects a device register (through the Comm byte), sends
143	1 to 31 bytes of data to it, and reads 1 to 31 bytes of data in return.
144	
145	S Addr Wr [A] Comm [A] Count [A] Data [A] ...
146	                             S Addr Rd [A] [Count] A [Data] ... A P
147	
148	
149	SMBus Host Notify
150	=================
151	
152	This command is sent from a SMBus device acting as a master to the
153	SMBus host acting as a slave.
154	It is the same form as Write Word, with the command code replaced by the
155	alerting device's address.
156	
157	[S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]
158	
159	
160	Packet Error Checking (PEC)
161	===========================
162	Packet Error Checking was introduced in Revision 1.1 of the specification.
163	
164	PEC adds a CRC-8 error-checking byte to all transfers.
165	
166	
167	Address Resolution Protocol (ARP)
168	=================================
169	The Address Resolution Protocol was introduced in Revision 2.0 of
170	the specification. It is a higher-layer protocol which uses the
171	messages above.
172	
173	ARP adds device enumeration and dynamic address assignment to
174	the protocol. All ARP communications use slave address 0x61 and
175	require PEC checksums.
176	
177	
178	I2C Block Transactions
179	======================
180	The following I2C block transactions are supported by the
181	SMBus layer and are described here for completeness.
182	I2C block transactions do not limit the number of bytes transferred
183	but the SMBus layer places a limit of 32 bytes.
184	
185	
186	I2C Block Read
187	==============
188	
189	This command reads a block of bytes from a device, from a 
190	designated register that is specified through the Comm byte.
191	
192	S Addr Wr [A] Comm [A] 
193	           S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
194	
195	
196	I2C Block Read (2 Comm bytes)
197	=============================
198	
199	This command reads a block of bytes from a device, from a 
200	designated register that is specified through the two Comm bytes.
201	
202	S Addr Wr [A] Comm1 [A] Comm2 [A] 
203	           S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
204	
205	
206	I2C Block Write
207	===============
208	
209	The opposite of the Block Read command, this writes bytes to 
210	a device, to a designated register that is specified through the
211	Comm byte. Note that command lengths of 0, 2, or more bytes are
212	supported as they are indistinguishable from data.
213	
214	S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P
215	
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