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Based on kernel version 3.13. Page generated on 2014-01-20 22:04 EST.

1	       STMicroelectronics 10/100/1000 Synopsys Ethernet driver
3	Copyright (C) 2007-2013  STMicroelectronics Ltd
4	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
6	This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
7	(Synopsys IP blocks).
9	Currently this network device driver is for all STM embedded MAC/GMAC
10	(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
11	FF1152AMT0221 D1215994A VIRTEX FPGA board.
13	DWC Ether MAC 10/100/1000 Universal version 3.70a (and older) and DWC Ether
14	MAC 10/100 Universal version 4.0 have been used for developing this driver.
16	This driver supports both the platform bus and PCI.
18	Please, for more information also visit: www.stlinux.com
20	1) Kernel Configuration
21	The kernel configuration option is STMMAC_ETH:
22	 Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) --->
23	 STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH)
25	2) Driver parameters list:
26		debug: message level (0: no output, 16: all);
27		phyaddr: to manually provide the physical address to the PHY device;
28		dma_rxsize: DMA rx ring size;
29		dma_txsize: DMA tx ring size;
30		buf_sz: DMA buffer size;
31		tc: control the HW FIFO threshold;
32		watchdog: transmit timeout (in milliseconds);
33		flow_ctrl: Flow control ability [on/off];
34		pause: Flow Control Pause Time;
35		eee_timer: tx EEE timer;
36		chain_mode: select chain mode instead of ring.
38	3) Command line options
39	Driver parameters can be also passed in command line by using:
40		stmmaceth=dma_rxsize:128,dma_txsize:512
42	4) Driver information and notes
44	4.1) Transmit process
45	The xmit method is invoked when the kernel needs to transmit a packet; it sets
46	the descriptors in the ring and informs the DMA engine that there is a packet
47	ready to be transmitted.
48	Once the controller has finished transmitting the packet, an interrupt is
49	triggered; So the driver will be able to release the socket buffers.
50	By default, the driver sets the NETIF_F_SG bit in the features field of the
51	net_device structure enabling the scatter/gather feature.
53	4.2) Receive process
54	When one or more packets are received, an interrupt happens. The interrupts
55	are not queued so the driver has to scan all the descriptors in the ring during
56	the receive process.
57	This is based on NAPI so the interrupt handler signals only if there is work
58	to be done, and it exits.
59	Then the poll method will be scheduled at some future point.
60	The incoming packets are stored, by the DMA, in a list of pre-allocated socket
61	buffers in order to avoid the memcpy (Zero-copy).
63	4.3) Interrupt Mitigation
64	The driver is able to mitigate the number of its DMA interrupts
65	using NAPI for the reception on chips older than the 3.50.
66	New chips have an HW RX-Watchdog used for this mitigation.
68	On Tx-side, the mitigation schema is based on a SW timer that calls the
69	tx function (stmmac_tx) to reclaim the resource after transmitting the
70	frames.
71	Also there is another parameter (like a threshold) used to program
72	the descriptors avoiding to set the interrupt on completion bit in
73	when the frame is sent (xmit).
75	Mitigation parameters can be tuned by ethtool.
77	4.4) WOL
78	Wake up on Lan feature through Magic and Unicast frames are supported for the
79	GMAC core.
81	4.5) DMA descriptors
82	Driver handles both normal and enhanced descriptors. The latter has been only
83	tested on DWC Ether MAC 10/100/1000 Universal version 3.41a and later.
85	STMMAC supports DMA descriptor to operate both in dual buffer (RING)
86	and linked-list(CHAINED) mode. In RING each descriptor points to two
87	data buffer pointers whereas in CHAINED mode they point to only one data
88	buffer pointer. RING mode is the default.
90	In CHAINED mode each descriptor will have pointer to next descriptor in
91	the list, hence creating the explicit chaining in the descriptor itself,
92	whereas such explicit chaining is not possible in RING mode.
94	4.6) Ethtool support
95	Ethtool is supported. Driver statistics and internal errors can be taken using:
96	ethtool -S ethX command. It is possible to dump registers etc.
98	4.7) Jumbo and Segmentation Offloading
99	Jumbo frames are supported and tested for the GMAC.
100	The GSO has been also added but it's performed in software.
101	LRO is not supported.
103	4.8) Physical
104	The driver is compatible with PAL to work with PHY and GPHY devices.
106	4.9) Platform information
107	Several driver's information can be passed through the platform
108	These are included in the include/linux/stmmac.h header file
109	and detailed below as well:
111	struct plat_stmmacenet_data {
112		char *phy_bus_name;
113		int bus_id;
114		int phy_addr;
115		int interface;
116		struct stmmac_mdio_bus_data *mdio_bus_data;
117		struct stmmac_dma_cfg *dma_cfg;
118		int clk_csr;
119		int has_gmac;
120		int enh_desc;
121		int tx_coe;
122		int rx_coe;
123		int bugged_jumbo;
124		int pmt;
125		int force_sf_dma_mode;
126		int force_thresh_dma_mode;
127		int riwt_off;
128		void (*fix_mac_speed)(void *priv, unsigned int speed);
129		void (*bus_setup)(void __iomem *ioaddr);
130		int (*init)(struct platform_device *pdev);
131		void (*exit)(struct platform_device *pdev);
132		void *custom_cfg;
133		void *custom_data;
134		void *bsp_priv;
135	 };
137	Where:
138	 o phy_bus_name: phy bus name to attach to the stmmac.
139	 o bus_id: bus identifier.
140	 o phy_addr: the physical address can be passed from the platform.
141		    If it is set to -1 the driver will automatically
142		    detect it at run-time by probing all the 32 addresses.
143	 o interface: PHY device's interface.
144	 o mdio_bus_data: specific platform fields for the MDIO bus.
145	 o dma_cfg: internal DMA parameters
146	   o pbl: the Programmable Burst Length is maximum number of beats to
147	       be transferred in one DMA transaction.
148	       GMAC also enables the 4xPBL by default.
149	   o fixed_burst/mixed_burst/burst_len
150	 o clk_csr: fixed CSR Clock range selection.
151	 o has_gmac: uses the GMAC core.
152	 o enh_desc: if sets the MAC will use the enhanced descriptor structure.
153	 o tx_coe: core is able to perform the tx csum in HW.
154	 o rx_coe: the supports three check sum offloading engine types:
155		   type_1, type_2 (full csum) and no RX coe.
156	 o bugged_jumbo: some HWs are not able to perform the csum in HW for
157			over-sized frames due to limited buffer sizes.
158			Setting this flag the csum will be done in SW on
159			JUMBO frames.
160	 o pmt: core has the embedded power module (optional).
161	 o force_sf_dma_mode: force DMA to use the Store and Forward mode
162			     instead of the Threshold.
163	 o force_thresh_dma_mode: force DMA to use the Threshold mode other than
164			     the Store and Forward mode.
165	 o riwt_off: force to disable the RX watchdog feature and switch to NAPI mode.
166	 o fix_mac_speed: this callback is used for modifying some syscfg registers
167			 (on ST SoCs) according to the link speed negotiated by the
168			 physical layer .
169	 o bus_setup: perform HW setup of the bus. For example, on some ST platforms
170		     this field is used to configure the AMBA  bridge to generate more
171		     efficient STBus traffic.
172	 o init/exit: callbacks used for calling a custom initialization;
173		     this is sometime necessary on some platforms (e.g. ST boxes)
174		     where the HW needs to have set some PIO lines or system cfg
175		     registers.
176	 o custom_cfg/custom_data: this is a custom configuration that can be passed
177				   while initializing the resources.
178	 o bsp_priv: another private pointer.
180	For MDIO bus The we have:
182	 struct stmmac_mdio_bus_data {
183		int (*phy_reset)(void *priv);
184		unsigned int phy_mask;
185		int *irqs;
186		int probed_phy_irq;
187	 };
189	Where:
190	 o phy_reset: hook to reset the phy device attached to the bus.
191	 o phy_mask: phy mask passed when register the MDIO bus within the driver.
192	 o irqs: list of IRQs, one per PHY.
193	 o probed_phy_irq: if irqs is NULL, use this for probed PHY.
195	For DMA engine we have the following internal fields that should be
196	tuned according to the HW capabilities.
198	struct stmmac_dma_cfg {
199		int pbl;
200		int fixed_burst;
201		int burst_len_supported;
202	};
204	Where:
205	 o pbl: Programmable Burst Length
206	 o fixed_burst: program the DMA to use the fixed burst mode
207	 o burst_len: this is the value we put in the register
208		      supported values are provided as macros in
209		      linux/stmmac.h header file.
211	---
213	Below an example how the structures above are using on ST platforms.
215	 static struct plat_stmmacenet_data stxYYY_ethernet_platform_data = {
216		.has_gmac = 0,
217		.enh_desc = 0,
218		.fix_mac_speed = stxYYY_ethernet_fix_mac_speed,
219					|
220					|-> to write an internal syscfg
221					|   on this platform when the
222					|   link speed changes from 10 to
223					|   100 and viceversa
224		.init = &stmmac_claim_resource,
225					|
226					|-> On ST SoC this calls own "PAD"
227					|   manager framework to claim
228					|   all the resources necessary
229					|   (GPIO ...). The .custom_cfg field
230					|   is used to pass a custom config.
231	};
233	Below the usage of the stmmac_mdio_bus_data: on this SoC, in fact,
234	there are two MAC cores: one MAC is for MDIO Bus/PHY emulation
235	with fixed_link support.
237	static struct stmmac_mdio_bus_data stmmac1_mdio_bus = {
238		.phy_reset = phy_reset;
239			|
240			|-> function to provide the phy_reset on this board
241		.phy_mask = 0,
242	};
244	static struct fixed_phy_status stmmac0_fixed_phy_status = {
245		.link = 1,
246		.speed = 100,
247		.duplex = 1,
248	};
250	During the board's device_init we can configure the first
251	MAC for fixed_link by calling:
252	  fixed_phy_add(PHY_POLL, 1, &stmmac0_fixed_phy_status));)
253	and the second one, with a real PHY device attached to the bus,
254	by using the stmmac_mdio_bus_data structure (to provide the id, the
255	reset procedure etc).
257	4.10) List of source files:
258	 o Kconfig
259	 o Makefile
260	 o stmmac_main.c: main network device driver;
261	 o stmmac_mdio.c: mdio functions;
262	 o stmmac_pci: PCI driver;
263	 o stmmac_platform.c: platform driver
264	 o stmmac_ethtool.c: ethtool support;
265	 o stmmac_timer.[ch]: timer code used for mitigating the driver dma interrupts
266			      (only tested on ST40 platforms based);
267	 o stmmac.h: private driver structure;
268	 o common.h: common definitions and VFTs;
269	 o descs.h: descriptor structure definitions;
270	 o dwmac1000_core.c: GMAC core functions;
271	 o dwmac1000_dma.c:  dma functions for the GMAC chip;
272	 o dwmac1000.h: specific header file for the GMAC;
273	 o dwmac100_core: MAC 100 core and dma code;
274	 o dwmac100_dma.c: dma functions for the MAC chip;
275	 o dwmac1000.h: specific header file for the MAC;
276	 o dwmac_lib.c: generic DMA functions shared among chips;
277	 o enh_desc.c: functions for handling enhanced descriptors;
278	 o norm_desc.c: functions for handling normal descriptors;
279	 o chain_mode.c/ring_mode.c:: functions to manage RING/CHAINED modes;
280	 o mmc_core.c/mmc.h: Management MAC Counters;
281	 o stmmac_hwtstamp.c: HW timestamp support for PTP
282	 o stmmac_ptp.c: PTP 1588 clock
284	5) Debug Information
286	The driver exports many information i.e. internal statistics,
287	debug information, MAC and DMA registers etc.
289	These can be read in several ways depending on the
290	type of the information actually needed.
292	For example a user can be use the ethtool support
293	to get statistics: e.g. using: ethtool -S ethX
294	(that shows the Management counters (MMC) if supported)
295	or sees the MAC/DMA registers: e.g. using: ethtool -d ethX
297	Compiling the Kernel with CONFIG_DEBUG_FS and enabling the
298	STMMAC_DEBUG_FS option the driver will export the following
299	debugfs entries:
301	/sys/kernel/debug/stmmaceth/descriptors_status
302	  To show the DMA TX/RX descriptor rings
304	Developer can also use the "debug" module parameter to get
305	further debug information.
307	In the end, there are other macros (that cannot be enabled
308	via menuconfig) to turn-on the RX/TX DMA debugging,
309	specific MAC core debug printk etc. Others to enable the
310	debug in the TX and RX processes.
311	All these are only useful during the developing stage
312	and should never enabled inside the code for general usage.
313	In fact, these can generate an huge amount of debug messages.
315	6) Energy Efficient Ethernet
317	Energy Efficient Ethernet(EEE) enables IEEE 802.3 MAC sublayer along
318	with a family of Physical layer to operate in the Low power Idle(LPI)
319	mode. The EEE mode supports the IEEE 802.3 MAC operation at 100Mbps,
320	1000Mbps & 10Gbps.
322	The LPI mode allows power saving by switching off parts of the
323	communication device functionality when there is no data to be
324	transmitted & received. The system on both the side of the link can
325	disable some functionalities & save power during the period of low-link
326	utilization. The MAC controls whether the system should enter or exit
327	the LPI mode & communicate this to PHY.
329	As soon as the interface is opened, the driver verifies if the EEE can
330	be supported. This is done by looking at both the DMA HW capability
331	register and the PHY devices MCD registers.
332	To enter in Tx LPI mode the driver needs to have a software timer
333	that enable and disable the LPI mode when there is nothing to be
334	transmitted.
336	7) Extended descriptors
337	The extended descriptors give us information about the receive Ethernet payload
338	when it is carrying PTP packets or TCP/UDP/ICMP over IP.
339	These are not available on GMAC Synopsys chips older than the 3.50.
340	At probe time the driver will decide if these can be actually used.
341	This support also is mandatory for PTPv2 because the extra descriptors 6 and 7
342	are used for saving the hardware timestamps.
344	8) Precision Time Protocol (PTP)
345	The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP),
346	which enables precise synchronization of clocks in measurement and
347	control systems implemented with technologies such as network
348	communication.
350	In addition to the basic timestamp features mentioned in IEEE 1588-2002
351	Timestamps, new GMAC cores support the advanced timestamp features.
352	IEEE 1588-2008 that can be enabled when configure the Kernel.
354	9) SGMII/RGMII supports
355	New GMAC devices provide own way to manage RGMII/SGMII.
356	This information is available at run-time by looking at the
357	HW capability register. This means that the stmmac can manage
358	auto-negotiation and link status w/o using the PHYLIB stuff
359	In fact, the HW provides a subset of extended registers to
360	restart the ANE, verify Full/Half duplex mode and Speed.
361	Also thanks to these registers it is possible to look at the
362	Auto-negotiated Link Parter Ability.
364	10) TODO:
365	 o XGMAC is not supported.
366	 o Complete the TBI & RTBI support.
367	 o extend VLAN support for 3.70a SYNP GMAC.
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