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Documentation / devicetree / bindings / gpio / gpio-bcm-kona.txt




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Based on kernel version 3.15.4. Page generated on 2014-07-07 09:00 EST.

1	Broadcom Kona Family GPIO
2	=========================
3	
4	This GPIO driver is used in the following Broadcom SoCs:
5	  BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
6	
7	The Broadcom GPIO Controller IP can be configured prior to synthesis to
8	support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
9	GPIO controller only supports edge, not level, triggering of interrupts.
10	
11	Required properties
12	-------------------
13	
14	- compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio"
15	- reg: Physical base address and length of the controller's registers.
16	- interrupts: The interrupt outputs from the controller. There is one GPIO
17	  interrupt per GPIO bank. The number of interrupts listed depends on the
18	  number of GPIO banks on the SoC. The interrupts must be ordered by bank,
19	  starting with bank 0. There is always a 1:1 mapping between banks and
20	  IRQs.
21	- #gpio-cells: Should be <2>. The first cell is the pin number, the second
22	  cell is used to specify optional parameters:
23	  - bit 0 specifies polarity (0 for normal, 1 for inverted)
24	  See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
25	- #interrupt-cells: Should be <2>. The first cell is the GPIO number. The
26	  second cell is used to specify flags. The following subset of flags is
27	  supported:
28	  - trigger type (bits[1:0]):
29	      1 = low-to-high edge triggered.
30	      2 = high-to-low edge triggered.
31	      3 = low-to-high or high-to-low edge triggered
32	      Valid values are 1, 2, 3
33	  See also .../devicetree/bindings/interrupt-controller/interrupts.txt.
34	- gpio-controller: Marks the device node as a GPIO controller.
35	- interrupt-controller: Marks the device node as an interrupt controller.
36	
37	Example:
38		gpio: gpio@35003000 {
39			compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
40			reg = <0x35003000 0x800>;
41			interrupts =
42			       <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
43				GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
44				GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
45				GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
46				GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
47				GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
48			#gpio-cells = <2>;
49			#interrupt-cells = <2>;
50			gpio-controller;
51			interrupt-controller;
52		};
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