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Documentation / devicetree / bindings / phy / samsung-phy.txt




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Based on kernel version 3.19. Page generated on 2015-02-13 21:18 EST.

1	Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY
2	-------------------------------------------------
3	
4	Required properties:
5	- compatible : should be "samsung,s5pv210-mipi-video-phy";
6	- reg : offset and length of the MIPI DPHY register set;
7	- #phy-cells : from the generic phy bindings, must be 1;
8	
9	For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
10	the PHY specifier identifies the PHY and its meaning is as follows:
11	  0 - MIPI CSIS 0,
12	  1 - MIPI DSIM 0,
13	  2 - MIPI CSIS 1,
14	  3 - MIPI DSIM 1.
15	
16	Samsung EXYNOS SoC series Display Port PHY
17	-------------------------------------------------
18	
19	Required properties:
20	- compatible : should be one of the following supported values:
21		 - "samsung,exynos5250-dp-video-phy"
22		 - "samsung,exynos5420-dp-video-phy"
23	- samsung,pmu-syscon: phandle for PMU system controller interface, used to
24			      control pmu registers for power isolation.
25	- #phy-cells : from the generic PHY bindings, must be 0;
26	
27	Samsung S5P/EXYNOS SoC series USB PHY
28	-------------------------------------------------
29	
30	Required properties:
31	- compatible : should be one of the listed compatibles:
32		- "samsung,exynos3250-usb2-phy"
33		- "samsung,exynos4210-usb2-phy"
34		- "samsung,exynos4x12-usb2-phy"
35		- "samsung,exynos5250-usb2-phy"
36		- "samsung,s5pv210-usb2-phy"
37	- reg : a list of registers used by phy driver
38		- first and obligatory is the location of phy modules registers
39	- samsung,sysreg-phandle - handle to syscon used to control the system registers
40	- samsung,pmureg-phandle - handle to syscon used to control PMU registers
41	- #phy-cells : from the generic phy bindings, must be 1;
42	- clocks and clock-names:
43		- the "phy" clock is required by the phy module, used as a gate
44		- the "ref" clock is used to get the rate of the clock provided to the
45		  PHY module
46	
47	The first phandle argument in the PHY specifier identifies the PHY, its
48	meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
49	and Exynos 4212) it is as follows:
50	  0 - USB device ("device"),
51	  1 - USB host ("host"),
52	  2 - HSIC0 ("hsic0"),
53	  3 - HSIC1 ("hsic1"),
54	Exynos3250 has only USB device phy available as phy 0.
55	
56	Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
57	register is supplied.
58	
59	Example:
60	
61	For Exynos 4412 (compatible with Exynos 4212):
62	
63	usbphy: phy@125b0000 {
64		compatible = "samsung,exynos4x12-usb2-phy";
65		reg = <0x125b0000 0x100>;
66		clocks = <&clock 305>, <&clock 2>;
67		clock-names = "phy", "ref";
68		status = "okay";
69		#phy-cells = <1>;
70		samsung,sysreg-phandle = <&sys_reg>;
71		samsung,pmureg-phandle = <&pmu_reg>;
72	};
73	
74	Then the PHY can be used in other nodes such as:
75	
76	phy-consumer@12340000 {
77		phys = <&usbphy 2>;
78		phy-names = "phy";
79	};
80	
81	Refer to DT bindings documentation of particular PHY consumer devices for more
82	information about required PHYs and the way of specification.
83	
84	Samsung SATA PHY Controller
85	---------------------------
86	
87	SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
88	Each SATA PHY controller should have its own node.
89	
90	Required properties:
91	- compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
92	- reg : offset and length of the SATA PHY register set;
93	- #phy-cells : must be zero
94	- clocks : must be exactly one entry
95	- clock-names : must be "sata_phyctrl"
96	- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
97	- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
98	
99	Example:
100		sata_phy: sata-phy@12170000 {
101			compatible = "samsung,exynos5250-sata-phy";
102			reg = <0x12170000 0x1ff>;
103			clocks = <&clock 287>;
104			clock-names = "sata_phyctrl";
105			#phy-cells = <0>;
106			samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
107			samsung,syscon-phandle = <&pmu_syscon>;
108		};
109	
110	Device-Tree bindings for sataphy i2c client driver
111	--------------------------------------------------
112	
113	Required properties:
114	compatible: Should be "samsung,exynos-sataphy-i2c"
115	- reg: I2C address of the sataphy i2c device.
116	
117	Example:
118	
119		sata_phy_i2c:sata-phy@38 {
120			compatible = "samsung,exynos-sataphy-i2c";
121			reg = <0x38>;
122		};
123	
124	Samsung Exynos5 SoC series USB DRD PHY controller
125	--------------------------------------------------
126	
127	Required properties:
128	- compatible : Should be set to one of the following supported values:
129		- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
130		- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
131		- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
132	- reg : Register offset and length of USB DRD PHY register set;
133	- clocks: Clock IDs array as required by the controller
134	- clock-names: names of clocks correseponding to IDs in the clock property;
135		       Required clocks:
136		- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
137		       used for register access.
138		- ref: PHY's reference clock (usually crystal clock), used for
139		       PHY operations, associated by phy name. It is used to
140		       determine bit values for clock settings register.
141		       For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
142		- optional clocks: Exynos7 SoC has now following additional
143				   gate clocks available:
144				   - phy_pipe: for PIPE3 phy
145				   - phy_utmi: for UTMI+ phy
146				   - itp: for ITP generation
147	- samsung,pmu-syscon: phandle for PMU system controller interface, used to
148			      control pmu registers for power isolation.
149	- #phy-cells : from the generic PHY bindings, must be 1;
150	
151	For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
152	compatible PHYs, the second cell in the PHY specifier identifies the
153	PHY id, which is interpreted as follows:
154	  0 - UTMI+ type phy,
155	  1 - PIPE3 type phy,
156	
157	Example:
158		usbdrd_phy: usbphy@12100000 {
159			compatible = "samsung,exynos5250-usbdrd-phy";
160			reg = <0x12100000 0x100>;
161			clocks = <&clock 286>, <&clock 1>;
162			clock-names = "phy", "ref";
163			samsung,pmu-syscon = <&pmu_system_controller>;
164			#phy-cells = <1>;
165		};
166	
167	- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
168		   'usbdrd_phy' nodes should have numbered alias in the aliases node,
169		   in the form of usbdrdphyN, N = 0, 1... (depending on number of
170		   controllers).
171	Example:
172		aliases {
173			usbdrdphy0 = &usb3_phy0;
174			usbdrdphy1 = &usb3_phy1;
175		};
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