Based on kernel version 6.1.49
. Page generated on 2023-08-29 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block maintainers: - Iskren Chernev <iskren.chernev@gmail.com> description: This binding describes the Top Level Mode Multiplexer block found in the SM4250/6115 platforms. properties: compatible: const: qcom,sm6115-tlmm reg: minItems: 3 maxItems: 3 reg-names: items: - const: west - const: south - const: east interrupts: description: Specifies the TLMM summary IRQ maxItems: 1 interrupt-controller: true '#interrupt-cells': description: Specifies the PIN numbers and Flags, as defined in defined in include/dt-bindings/interrupt-controller/irq.h const: 2 gpio-controller: true '#gpio-cells': description: Specifying the pin number and flags, as defined in include/dt-bindings/gpio/gpio.h const: 2 gpio-ranges: maxItems: 1 gpio-reserved-ranges: true wakeup-parent: true #PIN CONFIGURATION NODES patternProperties: '-state$': oneOf: - $ref: "#/$defs/qcom-sm6115-tlmm-state" - patternProperties: "-pins$": $ref: "#/$defs/qcom-sm6115-tlmm-state" additionalProperties: false '$defs': qcom-sm6115-tlmm-state: type: object description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. properties: pins: description: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] minItems: 1 maxItems: 36 function: description: Specify the alternative function to be configured for the specified pins. enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c, cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist, mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte, m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag, pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, elan1_adc1 ] drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] default: 2 description: Selects the drive strength for the specified pins, in mA. bias-pull-down: true bias-pull-up: true bias-disable: true output-high: true output-low: true required: - pins allOf: - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" - if: properties: pins: pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" then: required: - function additionalProperties: false allOf: - $ref: "pinctrl.yaml#" required: - compatible - reg - reg-names - interrupts - interrupt-controller - '#interrupt-cells' - gpio-controller - '#gpio-cells' - gpio-ranges additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> tlmm: pinctrl@500000 { compatible = "qcom,sm6115-tlmm"; reg = <0x500000 0x400000>, <0x900000 0x400000>, <0xd00000 0x400000>; reg-names = "west", "south", "east"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 114>; sdc2_on_state: sdc2-on-state { clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; sd-cd-pins { pins = "gpio88"; function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; }; |