Based on kernel version 6.1.49
. Page generated on 2023-08-29 08:21 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. SM8350 TLMM block maintainers: - Vinod Koul <vkoul@kernel.org> description: | This binding describes the Top Level Mode Multiplexer (TLMM) block found in the SM8350 platform. allOf: - $ref: "pinctrl.yaml#" - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# properties: compatible: const: qcom,sm8350-tlmm reg: maxItems: 1 interrupts: true interrupt-controller: true '#interrupt-cells': true gpio-controller: true gpio-reserved-ranges: true '#gpio-cells': true gpio-ranges: true wakeup-parent: true required: - compatible - reg additionalProperties: false patternProperties: '-state$': oneOf: - $ref: "#/$defs/qcom-sm8350-tlmm-state" - patternProperties: "-pins$": $ref: "#/$defs/qcom-sm8350-tlmm-state" additionalProperties: false $defs: qcom-sm8350-tlmm-state: type: object description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. properties: pins: description: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$" - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 function: description: Specify the alternative function to be configured for the specified pins. enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] bias-disable: true bias-pull-down: true bias-pull-up: true drive-strength: true input-enable: true output-high: true output-low: true required: - pins allOf: - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" - if: properties: pins: pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$" then: required: - function additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> pinctrl@f100000 { compatible = "qcom,sm8350-tlmm"; reg = <0x0f100000 0x300000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 203>; gpio-wo-subnode-state { pins = "gpio1"; function = "gpio"; }; uart-w-subnodes-state { rx-pins { pins = "gpio18"; function = "qup3"; bias-pull-up; }; tx-pins { pins = "gpio19"; function = "qup3"; bias-disable; }; }; }; ... |