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Documentation / devicetree / bindings / clock / vt8500.txt




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Based on kernel version 3.9. Page generated on 2013-05-02 22:57 EST.

1	Device Tree Clock bindings for arch-vt8500
2	
3	This binding uses the common clock binding[1].
4	
5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6	
7	Required properties:
8	- compatible : shall be one of the following:
9		"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10		"wm,wm8650-pll-clock" - for a WM8650 PLL clock
11		"via,vt8500-device-clock" - for a VT/WM device clock
12	
13	Required properties for PLL clocks:
14	- reg : shall be the control register offset from PMC base for the pll clock.
15	- clocks : shall be the input parent clock phandle for the clock. This should
16		be the reference clock.
17	- #clock-cells : from common clock binding; shall be set to 0.
18	
19	Required properties for device clocks:
20	- clocks : shall be the input parent clock phandle for the clock. This should
21		be a pll output.
22	- #clock-cells : from common clock binding; shall be set to 0.
23	
24	
25	Device Clocks
26	
27	Device clocks are required to have one or both of the following sets of
28	properties:
29	
30	
31	Gated device clocks:
32	
33	Required properties:
34	- enable-reg : shall be the register offset from PMC base for the enable
35		register.
36	- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
37	
38	
39	Divisor device clocks:
40	
41	Required property:
42	- divisor-reg : shall be the register offset from PMC base for the divisor
43		register.
44	Optional property:
45	- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
46		if not specified.
47	
48	
49	For example:
50	
51	ref25: ref25M {
52		#clock-cells = <0>;
53		compatible = "fixed-clock";
54		clock-frequency = <25000000>;
55	};
56	
57	plla: plla {
58		#clock-cells = <0>;
59		compatible = "wm,wm8650-pll-clock";
60		clocks = <&ref25>;
61		reg = <0x200>;
62	};
63	
64	sdhc: sdhc {
65		#clock-cells = <0>;
66		compatible = "via,vt8500-device-clock";
67		clocks = <&pllb>;
68		divisor-reg = <0x328>;
69		divisor-mask = <0x3f>;
70		enable-reg = <0x254>;
71		enable-bit = <18>;
72	};
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