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Documentation / devicetree / bindings / clock / vt8500.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	Device Tree Clock bindings for arch-vt8500
2	
3	This binding uses the common clock binding[1].
4	
5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6	
7	Required properties:
8	- compatible : shall be one of the following:
9		"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10		"wm,wm8650-pll-clock" - for a WM8650 PLL clock
11		"wm,wm8750-pll-clock" - for a WM8750 PLL clock
12		"wm,wm8850-pll-clock" - for a WM8850 PLL clock
13		"via,vt8500-device-clock" - for a VT/WM device clock
14	
15	Required properties for PLL clocks:
16	- reg : shall be the control register offset from PMC base for the pll clock.
17	- clocks : shall be the input parent clock phandle for the clock. This should
18		be the reference clock.
19	- #clock-cells : from common clock binding; shall be set to 0.
20	
21	Required properties for device clocks:
22	- clocks : shall be the input parent clock phandle for the clock. This should
23		be a pll output.
24	- #clock-cells : from common clock binding; shall be set to 0.
25	
26	
27	Device Clocks
28	
29	Device clocks are required to have one or both of the following sets of
30	properties:
31	
32	
33	Gated device clocks:
34	
35	Required properties:
36	- enable-reg : shall be the register offset from PMC base for the enable
37		register.
38	- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
39	
40	
41	Divisor device clocks:
42	
43	Required property:
44	- divisor-reg : shall be the register offset from PMC base for the divisor
45		register.
46	Optional property:
47	- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
48		if not specified.
49	
50	
51	For example:
52	
53	ref25: ref25M {
54		#clock-cells = <0>;
55		compatible = "fixed-clock";
56		clock-frequency = <25000000>;
57	};
58	
59	plla: plla {
60		#clock-cells = <0>;
61		compatible = "wm,wm8650-pll-clock";
62		clocks = <&ref25>;
63		reg = <0x200>;
64	};
65	
66	sdhc: sdhc {
67		#clock-cells = <0>;
68		compatible = "via,vt8500-device-clock";
69		clocks = <&pllb>;
70		divisor-reg = <0x328>;
71		divisor-mask = <0x3f>;
72		enable-reg = <0x254>;
73		enable-bit = <18>;
74	};
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