Based on kernel version 4.16.1. Page generated on 2018-04-09 11:52 EST.
1 Allwinner NAND Flash Controller (NFC) 2 3 Required properties: 4 - compatible : "allwinner,sun4i-a10-nand". 5 - reg : shall contain registers location and length for data and reg. 6 - interrupts : shall define the nand controller interrupt. 7 - #address-cells: shall be set to 1. Encode the nand CS. 8 - #size-cells : shall be set to 0. 9 - clocks : shall reference nand controller clocks. 10 - clock-names : nand controller internal clock names. Shall contain : 11 * "ahb" : AHB gating clock 12 * "mod" : nand controller clock 13 14 Optional properties: 15 - dmas : shall reference DMA channel associated to the NAND controller. 16 - dma-names : shall be "rxtx". 17 18 Optional children nodes: 19 Children nodes represent the available nand chips. 20 21 Optional properties: 22 - reset : phandle + reset specifier pair 23 - reset-names : must contain "ahb" 24 - allwinner,rb : shall contain the native Ready/Busy ids. 25 or 26 - rb-gpios : shall contain the gpios used as R/B pins. 27 - nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft", 28 "soft_bch" or "none") 29 30 see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. 31 32 33 Examples: 34 nfc: nand@1c03000 { 35 compatible = "allwinner,sun4i-a10-nand"; 36 reg = <0x01c03000 0x1000>; 37 interrupts = <0 37 1>; 38 clocks = <&ahb_gates 13>, <&nand_clk>; 39 clock-names = "ahb", "mod"; 40 #address-cells = <1>; 41 #size-cells = <0>; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; 44 45 nand@0 { 46 reg = <0>; 47 allwinner,rb = <0>; 48 nand-ecc-mode = "soft_bch"; 49 }; 50 };