# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cortina Systems Gemini Ethernet Controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  This ethernet controller is found in the Gemini SoC family:
  StorLink SL3512 and SL3516, also known as Cortina Systems
  CS3512 and CS3516.

properties:
  compatible:
    const: cortina,gemini-ethernet

  reg:
    minItems: 3
    description: must contain the global registers and the V-bit and A-bit
      memory areas, in total three register sets.
 
  "#address-cells":
    const: 1
 
  "#size-cells":
    const: 1

  ranges: true
 
# The subnodes represents the two ethernet ports in this device.
# They are not independent of each other since they share resources
# in the parent node, and are thus children.
patternProperties:
  "^ethernet-port@[0-9]+$":
    type: object
    unevaluatedProperties: false
    description: contains the resources for ethernet port
    allOf:
      - $ref: ethernet-controller.yaml#
    properties:
      compatible:
        const: cortina,gemini-ethernet-port

      reg:
        items:
          - description: DMA/TOE memory
          - description: GMAC memory area of the port

      interrupts:
        maxItems: 1
        description: should contain the interrupt line of the port.
                     this is nominally a level interrupt active high.

      resets:
        maxItems: 1
        description: this must provide an SoC-integrated reset line for the port.

      clocks:
        maxItems: 1
        description: this should contain a handle to the PCLK clock for
                     clocking the silicon in this port

      clock-names:
        const: PCLK

    required:
      - reg
      - compatible
      - interrupts
      - resets
      - clocks
      - clock-names

required:
  - compatible
  - reg
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/cortina,gemini-clock.h>
    #include <dt-bindings/reset/cortina,gemini-reset.h>
    mdio0: mdio {
      #address-cells = <1>;
      #size-cells = <0>;
      phy0: ethernet-phy@1 {
        reg = <1>;
        device_type = "ethernet-phy";
      };
      phy1: ethernet-phy@3 {
        reg = <3>;
        device_type = "ethernet-phy";
      };
    };
 
 
    ethernet@60000000 {
        compatible = "cortina,gemini-ethernet";
        reg = <0x60000000 0x4000>, /* Global registers, queue */
              <0x60004000 0x2000>, /* V-bit */
              <0x60006000 0x2000>; /* A-bit */
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
 
        gmac0: ethernet-port@0 {
                compatible = "cortina,gemini-ethernet-port";
                reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
                      <0x6000a000 0x2000>; /* Port 0 GMAC */
                interrupt-parent = <&intcon>;
                interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
                resets = <&syscon GEMINI_RESET_GMAC0>;
                clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
                clock-names = "PCLK";
                phy-mode = "rgmii";
                phy-handle = <&phy0>;
        };
 
        gmac1: ethernet-port@1 {
                compatible = "cortina,gemini-ethernet-port";
                reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
                      <0x6000e000 0x2000>; /* Port 1 GMAC */
                interrupt-parent = <&intcon>;
                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
                resets = <&syscon GEMINI_RESET_GMAC1>;
                clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
                clock-names = "PCLK";
                phy-mode = "rgmii";
                phy-handle = <&phy1>;
        };
    };