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Documentation / devicetree / bindings / net / fsl-tsec-phy.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:01 EST.

1	* MDIO IO device
2	
3	The MDIO is a bus to which the PHY devices are connected.  For each
4	device that exists on this bus, a child node should be created.  See
5	the definition of the PHY node in booting-without-of.txt for an example
6	of how to define a PHY.
7	
8	Required properties:
9	  - reg : Offset and length of the register set for the device
10	  - compatible : Should define the compatible device type for the
11	    mdio.  Currently, this is most likely to be "fsl,gianfar-mdio"
12	
13	Example:
14	
15		mdio@24520 {
16			reg = <24520 20>;
17			compatible = "fsl,gianfar-mdio";
18	
19			ethernet-phy@0 {
20				......
21			};
22		};
23	
24	* TBI Internal MDIO bus
25	
26	As of this writing, every tsec is associated with an internal TBI PHY.
27	This PHY is accessed through the local MDIO bus.  These buses are defined
28	similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi".
29	The TBI PHYs underneath them are similar to normal PHYs, but the reg property
30	is considered instructive, rather than descriptive.  The reg property should
31	be chosen so it doesn't interfere with other PHYs on the bus.
32	
33	* Gianfar-compatible ethernet nodes
34	
35	Properties:
36	
37	  - device_type : Should be "network"
38	  - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
39	  - compatible : Should be "gianfar"
40	  - reg : Offset and length of the register set for the device
41	  - local-mac-address : List of bytes representing the ethernet address of
42	    this controller
43	  - interrupts : For FEC devices, the first interrupt is the device's
44	    interrupt.  For TSEC and eTSEC devices, the first interrupt is
45	    transmit, the second is receive, and the third is error.
46	  - phy-handle : The phandle for the PHY connected to this ethernet
47	    controller.
48	  - fixed-link : <a b c d e> where a is emulated phy id - choose any,
49	    but unique to the all specified fixed-links, b is duplex - 0 half,
50	    1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
51	    pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
52	  - phy-connection-type : a string naming the controller/PHY interface type,
53	    i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
54	    "tbi", or "rtbi".  This property is only really needed if the connection
55	    is of type "rgmii-id", as all other connection types are detected by
56	    hardware.
57	  - fsl,magic-packet : If present, indicates that the hardware supports
58	    waking up via magic packet.
59	  - bd-stash : If present, indicates that the hardware supports stashing
60	    buffer descriptors in the L2.
61	  - rx-stash-len : Denotes the number of bytes of a received buffer to stash
62	    in the L2.
63	  - rx-stash-idx : Denotes the index of the first byte from the received
64	    buffer to stash in the L2.
65	
66	Example:
67		ethernet@24000 {
68			device_type = "network";
69			model = "TSEC";
70			compatible = "gianfar";
71			reg = <0x24000 0x1000>;
72			local-mac-address = [ 00 E0 0C 00 73 00 ];
73			interrupts = <29 2 30 2 34 2>;
74			interrupt-parent = <&mpic>;
75			phy-handle = <&phy0>
76		};
77	
78	* Gianfar PTP clock nodes
79	
80	General Properties:
81	
82	  - compatible   Should be "fsl,etsec-ptp"
83	  - reg          Offset and length of the register set for the device
84	  - interrupts   There should be at least two interrupts. Some devices
85	                 have as many as four PTP related interrupts.
86	
87	Clock Properties:
88	
89	  - fsl,cksel        Timer reference clock source.
90	  - fsl,tclk-period  Timer reference clock period in nanoseconds.
91	  - fsl,tmr-prsc     Prescaler, divides the output clock.
92	  - fsl,tmr-add      Frequency compensation value.
93	  - fsl,tmr-fiper1   Fixed interval period pulse generator.
94	  - fsl,tmr-fiper2   Fixed interval period pulse generator.
95	  - fsl,max-adj      Maximum frequency adjustment in parts per billion.
96	
97	  These properties set the operational parameters for the PTP
98	  clock. You must choose these carefully for the clock to work right.
99	  Here is how to figure good values:
100	
101	  TimerOsc     = selected reference clock   MHz
102	  tclk_period  = desired clock period       nanoseconds
103	  NominalFreq  = 1000 / tclk_period         MHz
104	  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
105	  tmr_add      = ceil(2^32 / FreqDivRatio)
106	  OutputClock  = NominalFreq / tmr_prsc     MHz
107	  PulseWidth   = 1 / OutputClock            microseconds
108	  FiperFreq1   = desired frequency in Hz
109	  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
110	  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
111	  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1
112	
113	  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
114	  driver expects that tmr_fiper1 will be correctly set to produce a 1
115	  Pulse Per Second (PPS) signal, since this will be offered to the PPS
116	  subsystem to synchronize the Linux clock.
117	
118	  Reference clock source is determined by the value, which is holded
119	  in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
120	  value, which will be directly written in those bits, that is why,
121	  according to reference manual, the next clock sources can be used:
122	
123	  <0> - external high precision timer reference clock (TSEC_TMR_CLK
124	        input is used for this purpose);
125	  <1> - eTSEC system clock;
126	  <2> - eTSEC1 transmit clock;
127	  <3> - RTC clock input.
128	
129	  When this attribute is not used, eTSEC system clock will serve as
130	  IEEE 1588 timer reference clock.
131	
132	Example:
133	
134		ptp_clock@24E00 {
135			compatible = "fsl,etsec-ptp";
136			reg = <0x24E00 0xB0>;
137			interrupts = <12 0x8 13 0x8>;
138			interrupt-parent = < &ipic >;
139			fsl,cksel       = <1>;
140			fsl,tclk-period = <10>;
141			fsl,tmr-prsc    = <100>;
142			fsl,tmr-add     = <0x999999A4>;
143			fsl,tmr-fiper1  = <0x3B9AC9F6>;
144			fsl,tmr-fiper2  = <0x00018696>;
145			fsl,max-adj     = <659999998>;
146		};
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