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Documentation / devicetree / bindings / net / cpsw.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:01 EST.

1	TI SoC Ethernet Switch Controller Device Tree Bindings
2	------------------------------------------------------
3	
4	Required properties:
5	- compatible		: Should be "ti,cpsw"
6	- reg			: physical base address and size of the cpsw
7				  registers map
8	- interrupts		: property with a value describing the interrupt
9				  number
10	- interrupt-parent	: The parent interrupt controller
11	- cpdma_channels 	: Specifies number of channels in CPDMA
12	- ale_entries		: Specifies No of entries ALE can hold
13	- bd_ram_size		: Specifies internal descriptor RAM size
14	- rx_descs		: Specifies number of Rx descriptors
15	- mac_control		: Specifies Default MAC control register content
16				  for the specific platform
17	- slaves		: Specifies number for slaves
18	- active_slave		: Specifies the slave to use for time stamping,
19				  ethtool and SIOCGMIIPHY
20	- cpts_clock_mult	: Numerator to convert input clock ticks into nanoseconds
21	- cpts_clock_shift	: Denominator to convert input clock ticks into nanoseconds
22	
23	Optional properties:
24	- ti,hwmods		: Must be "cpgmac0"
25	- no_bd_ram		: Must be 0 or 1
26	- dual_emac		: Specifies Switch to act as Dual EMAC
27	
28	Slave Properties:
29	Required properties:
30	- phy_id		: Specifies slave phy id
31	- phy-mode		: The interface between the SoC and the PHY (a string
32				  that of_get_phy_mode() can understand)
33	- mac-address		: Specifies slave MAC address
34	
35	Optional properties:
36	- dual_emac_res_vlan	: Specifies VID to be used to segregate the ports
37	
38	Note: "ti,hwmods" field is used to fetch the base address and irq
39	resources from TI, omap hwmod data base during device registration.
40	Future plan is to migrate hwmod data base contents into device tree
41	blob so that, all the required data will be used from device tree dts
42	file.
43	
44	Examples:
45	
46		mac: ethernet@4A100000 {
47			compatible = "ti,cpsw";
48			reg = <0x4A100000 0x1000>;
49			interrupts = <55 0x4>;
50			interrupt-parent = <&intc>;
51			cpdma_channels = <8>;
52			ale_entries = <1024>;
53			bd_ram_size = <0x2000>;
54			no_bd_ram = <0>;
55			rx_descs = <64>;
56			mac_control = <0x20>;
57			slaves = <2>;
58			active_slave = <0>;
59			cpts_clock_mult = <0x80000000>;
60			cpts_clock_shift = <29>;
61			cpsw_emac0: slave@0 {
62				phy_id = <&davinci_mdio>, <0>;
63				phy-mode = "rgmii-txid";
64				/* Filled in by U-Boot */
65				mac-address = [ 00 00 00 00 00 00 ];
66			};
67			cpsw_emac1: slave@1 {
68				phy_id = <&davinci_mdio>, <1>;
69				phy-mode = "rgmii-txid";
70				/* Filled in by U-Boot */
71				mac-address = [ 00 00 00 00 00 00 ];
72			};
73		};
74	
75	(or)
76		mac: ethernet@4A100000 {
77			compatible = "ti,cpsw";
78			ti,hwmods = "cpgmac0";
79			cpdma_channels = <8>;
80			ale_entries = <1024>;
81			bd_ram_size = <0x2000>;
82			no_bd_ram = <0>;
83			rx_descs = <64>;
84			mac_control = <0x20>;
85			slaves = <2>;
86			active_slave = <0>;
87			cpts_clock_mult = <0x80000000>;
88			cpts_clock_shift = <29>;
89			cpsw_emac0: slave@0 {
90				phy_id = <&davinci_mdio>, <0>;
91				phy-mode = "rgmii-txid";
92				/* Filled in by U-Boot */
93				mac-address = [ 00 00 00 00 00 00 ];
94			};
95			cpsw_emac1: slave@1 {
96				phy_id = <&davinci_mdio>, <1>;
97				phy-mode = "rgmii-txid";
98				/* Filled in by U-Boot */
99				mac-address = [ 00 00 00 00 00 00 ];
100			};
101		};
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