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Documentation / devicetree / bindings / net / sti-dwmac.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:37 EST.

1	STMicroelectronics SoC DWMAC glue layer controller
2	
3	The device node has following properties.
4	
5	Required properties:
6	 - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac" or
7	   "st,stid127-dwmac".
8	 - reg		: Offset of the glue configuration register map in system
9	   configuration regmap pointed by st,syscon property and size.
10	
11	 - reg-names	: Should be "sti-ethconf".
12	
13	 - st,syscon	: Should be phandle to system configuration node which
14	   encompases this glue registers.
15	
16	 - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
17	   wired up in from different sources. One via TXCLK pin and other via CLK_125
18	   pin. This wiring is totally board dependent. However the retiming glue
19	   logic should be configured accordingly. Possible values for this property
20	
21		   "txclk" - if 125Mhz clock is wired up via txclk line.
22		   "clk_125" - if 125Mhz clock is wired up via clk_125 line.
23	
24	   This property is only valid for Giga bit setup( GMII, RGMII), and it is
25	   un-used for non-giga bit (MII and RMII) setups. Also note that internal
26	   clockgen can not generate stable 125Mhz clock.
27	
28	 - st,ext-phyclk: This boolean property indicates who is generating the clock
29	  for tx and rx. This property is only valid for RMII case where the clock can
30	  be generated from the MAC or PHY.
31	
32	 - clock-names: should be "sti-ethclk".
33	 - clocks: Should point to ethernet clockgen which can generate phyclk.
34	
35	
36	Example:
37	
38	ethernet0: dwmac@fe810000 {
39		device_type 	= "network";
40		compatible	= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
41		reg 		= <0xfe810000 0x8000>, <0x8bc 0x4>;
42		reg-names	= "stmmaceth", "sti-ethconf";
43		interrupts	= <0 133 0>, <0 134 0>, <0 135 0>;
44		interrupt-names	= "macirq", "eth_wake_irq", "eth_lpi";
45		phy-mode	= "mii";
46	
47		st,syscon	= <&syscfg_rear>;
48	
49		snps,pbl 	= <32>;
50		snps,mixed-burst;
51	
52		resets		= <&softreset STIH416_ETH0_SOFTRESET>;
53		reset-names	= "stmmaceth";
54		pinctrl-0	= <&pinctrl_mii0>;
55		pinctrl-names 	= "default";
56		clocks		= <&CLK_S_GMAC0_PHY>;
57		clock-names	= "stmmaceth";
58	};
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