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Documentation / devicetree / bindings / pinctrl / rockchip,pinctrl.txt




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Based on kernel version 4.3. Page generated on 2015-11-02 12:46 EST.

1	* Rockchip Pinmux Controller
2	
3	The Rockchip Pinmux Controller, enables the IC
4	to share one PAD to several functional blocks. The sharing is done by
5	multiplexing the PAD input/output signals. For each PAD there are several
6	muxing options with option 0 being the use as a GPIO.
7	
8	Please refer to pinctrl-bindings.txt in this directory for details of the
9	common pinctrl bindings used by client devices, including the meaning of the
10	phrase "pin configuration node".
11	
12	The Rockchip pin configuration node is a node of a group of pins which can be
13	used for a specific device or function. This node represents both mux and
14	config of the pins in that group. The 'pins' selects the function mode(also
15	named pin mode) this pin can work on and the 'config' configures various pad
16	settings such as pull-up, etc.
17	
18	The pins are grouped into up to 5 individual pin banks which need to be
19	defined as gpio sub-nodes of the pinmux controller.
20	
21	Required properties for iomux controller:
22	  - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
23			       "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
24			       "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
25	  - rockchip,grf: phandle referencing a syscon providing the
26		 "general register files"
27	
28	Optional properties for iomux controller:
29	  - rockchip,pmu: phandle referencing a syscon providing the pmu registers
30		 as some SoCs carry parts of the iomux controller registers there.
31		 Required for at least rk3188 and rk3288. On the rk3368 this should
32		 point to the PMUGRF syscon.
33	
34	Deprecated properties for iomux controller:
35	  - reg: first element is the general register space of the iomux controller
36		 It should be large enough to contain also separate pull registers.
37		 second element is the separate pull register space of the rk3188.
38		 Use rockchip,grf and rockchip,pmu described above instead.
39	
40	Required properties for gpio sub nodes:
41	  - compatible: "rockchip,gpio-bank"
42	  - reg: register of the gpio bank (different than the iomux registerset)
43	  - interrupts: base interrupt of the gpio bank in the interrupt controller
44	  - clocks: clock that drives this bank
45	  - gpio-controller: identifies the node as a gpio controller and pin bank.
46	  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
47	    binding is used, the amount of cells must be specified as 2. See generic
48	    GPIO binding documentation for description of particular cells.
49	  - interrupt-controller: identifies the controller node as interrupt-parent.
50	  - #interrupt-cells: the value of this property should be 2 and the interrupt
51	    cells should use the standard two-cell scheme described in
52	    bindings/interrupt-controller/interrupts.txt
53	
54	Deprecated properties for gpio sub nodes:
55	  - compatible: "rockchip,rk3188-gpio-bank0"
56	  - reg: second element: separate pull register for rk3188 bank0, use
57		 rockchip,pmu described above instead
58	
59	Required properties for pin configuration node:
60	  - rockchip,pins: 3 integers array, represents a group of pins mux and config
61	    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
62	    The MUX 0 means gpio and MUX 1 to N mean the specific device function.
63	    The phandle of a node containing the generic pinconfig options
64	    to use, as described in pinctrl-bindings.txt in this directory.
65	
66	Examples:
67	
68	#include <dt-bindings/pinctrl/rockchip.h>
69	
70	...
71	
72	pinctrl@20008000 {
73		compatible = "rockchip,rk3066a-pinctrl";
74		rockchip,grf = <&grf>;
75	
76		#address-cells = <1>;
77		#size-cells = <1>;
78		ranges;
79	
80		gpio0: gpio0@20034000 {
81			compatible = "rockchip,gpio-bank";
82			reg = <0x20034000 0x100>;
83			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
84			clocks = <&clk_gates8 9>;
85	
86			gpio-controller;
87			#gpio-cells = <2>;
88	
89			interrupt-controller;
90			#interrupt-cells = <2>;
91		};
92	
93		...
94	
95		pcfg_pull_default: pcfg_pull_default {
96			bias-pull-pin-default
97		};
98	
99		uart2 {
100			uart2_xfer: uart2-xfer {
101				rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
102						<RK_GPIO1 9 1 &pcfg_pull_default>;
103			};
104		};
105	};
106	
107	uart2: serial@20064000 {
108		compatible = "snps,dw-apb-uart";
109		reg = <0x20064000 0x400>;
110		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
111		reg-shift = <2>;
112		reg-io-width = <1>;
113		clocks = <&mux_uart2>;
114		status = "okay";
115	
116		pinctrl-names = "default";
117		pinctrl-0 = <&uart2_xfer>;
118	};
119	
120	Example for rk3188:
121	
122		pinctrl@20008000 {
123			compatible = "rockchip,rk3188-pinctrl";
124			rockchip,grf = <&grf>;
125			rockchip,pmu = <&pmu>;
126			#address-cells = <1>;
127			#size-cells = <1>;
128			ranges;
129	
130			gpio0: gpio0@0x2000a000 {
131				compatible = "rockchip,rk3188-gpio-bank0";
132				reg = <0x2000a000 0x100>;
133				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
134				clocks = <&clk_gates8 9>;
135	
136				gpio-controller;
137				#gpio-cells = <2>;
138	
139				interrupt-controller;
140				#interrupt-cells = <2>;
141			};
142	
143			gpio1: gpio1@0x2003c000 {
144				compatible = "rockchip,gpio-bank";
145				reg = <0x2003c000 0x100>;
146				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
147				clocks = <&clk_gates8 10>;
148	
149				gpio-controller;
150				#gpio-cells = <2>;
151	
152				interrupt-controller;
153				#interrupt-cells = <2>;
154			};
155	
156			...
157	
158		};
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