Documentation / devicetree / bindings / net / amlogic,g12a-mdio-mux.yaml


Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MDIO bus multiplexer/glue of Amlogic G12a SoC family

description:
  This is a special case of a MDIO bus multiplexer. It allows to choose between
  the internal mdio bus leading to the embedded 10/100 PHY or the external
  MDIO bus.

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

allOf:
  - $ref: mdio-mux.yaml#

properties:
  compatible:
    const: amlogic,g12a-mdio-mux

  reg:
    maxItems: 1

  clocks:
    items:
      - description: peripheral clock
      - description: platform crytal
      - description: SoC 50MHz MPLL

  clock-names:
    items:
      - const: pclk
      - const: clkin0
      - const: clkin1

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    mdio-multiplexer@4c000 {
        compatible = "amlogic,g12a-mdio-mux";
        reg = <0x4c000 0xa4>;
        clocks = <&clkc_eth_phy>, <&xtal>, <&clkc_mpll>;
        clock-names = "pclk", "clkin0", "clkin1";
        mdio-parent-bus = <&mdio0>;
        #address-cells = <1>;
        #size-cells = <0>;
 
        mdio@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;
        };
 
        mdio@1 {
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;
 
            ethernet-phy@8 {
                compatible = "ethernet-phy-id0180.3301",
                             "ethernet-phy-ieee802.3-c22";
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
                reg = <8>;
                max-speed = <100>;
            };
        };
    };
...