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Documentation / devicetree / bindings / arm / arch_timer.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:00 EST.

1	* ARM architected timer
2	
3	ARM cores may have a per-core architected timer, which provides per-cpu timers,
4	or a memory mapped architected timer, which provides up to 8 frames with a
5	physical and optional virtual timer per frame.
6	
7	The per-core architected timer is attached to a GIC to deliver its
8	per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
9	to deliver its interrupts via SPIs.
10	
11	** CP15 Timer node properties:
12	
13	- compatible : Should at least contain one of
14		"arm,armv7-timer"
15		"arm,armv8-timer"
16	
17	- interrupts : Interrupt list for secure, non-secure, virtual and
18	  hypervisor timers, in that order.
19	
20	- clock-frequency : The frequency of the main counter, in Hz. Optional.
21	
22	Example:
23	
24		timer {
25			compatible = "arm,cortex-a15-timer",
26				     "arm,armv7-timer";
27			interrupts = <1 13 0xf08>,
28				     <1 14 0xf08>,
29				     <1 11 0xf08>,
30				     <1 10 0xf08>;
31			clock-frequency = <100000000>;
32		};
33	
34	** Memory mapped timer node properties:
35	
36	- compatible : Should at least contain "arm,armv7-timer-mem".
37	
38	- clock-frequency : The frequency of the main counter, in Hz. Optional.
39	
40	- reg : The control frame base address.
41	
42	Note that #address-cells, #size-cells, and ranges shall be present to ensure
43	the CPU can address a frame's registers.
44	
45	A timer node has up to 8 frame sub-nodes, each with the following properties:
46	
47	- frame-number: 0 to 7.
48	
49	- interrupts : Interrupt list for physical and virtual timers in that order.
50	  The virtual timer interrupt is optional.
51	
52	- reg : The first and second view base addresses in that order. The second view
53	  base address is optional.
54	
55	- status : "disabled" indicates the frame is not available for use. Optional.
56	
57	Example:
58	
59		timer@f0000000 {
60			compatible = "arm,armv7-timer-mem";
61			#address-cells = <1>;
62			#size-cells = <1>;
63			ranges;
64			reg = <0xf0000000 0x1000>;
65			clock-frequency = <50000000>;
66	
67			frame@f0001000 {
68				frame-number = <0>
69				interrupts = <0 13 0x8>,
70					     <0 14 0x8>;
71				reg = <0xf0001000 0x1000>,
72				      <0xf0002000 0x1000>;
73			};
74	
75			frame@f0003000 {
76				frame-number = <1>
77				interrupts = <0 15 0x8>;
78				reg = <0xf0003000 0x1000>;
79				status = "disabled";
80			};
81		};
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