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Documentation / devicetree / bindings / arm / arch_timer.txt




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Based on kernel version 3.19. Page generated on 2015-02-13 21:16 EST.

1	* ARM architected timer
2	
3	ARM cores may have a per-core architected timer, which provides per-cpu timers,
4	or a memory mapped architected timer, which provides up to 8 frames with a
5	physical and optional virtual timer per frame.
6	
7	The per-core architected timer is attached to a GIC to deliver its
8	per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
9	to deliver its interrupts via SPIs.
10	
11	** CP15 Timer node properties:
12	
13	- compatible : Should at least contain one of
14		"arm,armv7-timer"
15		"arm,armv8-timer"
16	
17	- interrupts : Interrupt list for secure, non-secure, virtual and
18	  hypervisor timers, in that order.
19	
20	- clock-frequency : The frequency of the main counter, in Hz. Optional.
21	
22	- always-on : a boolean property. If present, the timer is powered through an
23	  always-on power domain, therefore it never loses context.
24	
25	** Optional properties:
26	
27	- arm,cpu-registers-not-fw-configured : Firmware does not initialize
28	  any of the generic timer CPU registers, which contain their
29	  architecturally-defined reset values. Only supported for 32-bit
30	  systems which follow the ARMv7 architected reset values.
31	
32	
33	Example:
34	
35		timer {
36			compatible = "arm,cortex-a15-timer",
37				     "arm,armv7-timer";
38			interrupts = <1 13 0xf08>,
39				     <1 14 0xf08>,
40				     <1 11 0xf08>,
41				     <1 10 0xf08>;
42			clock-frequency = <100000000>;
43		};
44	
45	** Memory mapped timer node properties:
46	
47	- compatible : Should at least contain "arm,armv7-timer-mem".
48	
49	- clock-frequency : The frequency of the main counter, in Hz. Optional.
50	
51	- reg : The control frame base address.
52	
53	Note that #address-cells, #size-cells, and ranges shall be present to ensure
54	the CPU can address a frame's registers.
55	
56	A timer node has up to 8 frame sub-nodes, each with the following properties:
57	
58	- frame-number: 0 to 7.
59	
60	- interrupts : Interrupt list for physical and virtual timers in that order.
61	  The virtual timer interrupt is optional.
62	
63	- reg : The first and second view base addresses in that order. The second view
64	  base address is optional.
65	
66	- status : "disabled" indicates the frame is not available for use. Optional.
67	
68	Example:
69	
70		timer@f0000000 {
71			compatible = "arm,armv7-timer-mem";
72			#address-cells = <1>;
73			#size-cells = <1>;
74			ranges;
75			reg = <0xf0000000 0x1000>;
76			clock-frequency = <50000000>;
77	
78			frame@f0001000 {
79				frame-number = <0>
80				interrupts = <0 13 0x8>,
81					     <0 14 0x8>;
82				reg = <0xf0001000 0x1000>,
83				      <0xf0002000 0x1000>;
84			};
85	
86			frame@f0003000 {
87				frame-number = <1>
88				interrupts = <0 15 0x8>;
89				reg = <0xf0003000 0x1000>;
90				status = "disabled";
91			};
92		};
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