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Documentation / devicetree / bindings / arm / cpus.txt




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Based on kernel version 3.19. Page generated on 2015-02-13 21:17 EST.

1	=================
2	ARM CPUs bindings
3	=================
4	
5	The device tree allows to describe the layout of CPUs in a system through
6	the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7	defining properties for every cpu.
8	
9	Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
10	
11	https://www.power.org/documentation/epapr-version-1-1/
12	
13	with updates for 32-bit and 64-bit ARM systems provided in this document.
14	
15	================================
16	Convention used in this document
17	================================
18	
19	This document follows the conventions described in the ePAPR v1.1, with
20	the addition:
21	
22	- square brackets define bitfields, eg reg[7:0] value of the bitfield in
23	  the reg property contained in bits 7 down to 0
24	
25	=====================================
26	cpus and cpu node bindings definition
27	=====================================
28	
29	The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30	nodes to be present and contain the properties described below.
31	
32	- cpus node
33	
34		Description: Container of cpu nodes
35	
36		The node name must be "cpus".
37	
38		A cpus node must define the following properties:
39	
40		- #address-cells
41			Usage: required
42			Value type: <u32>
43	
44			Definition depends on ARM architecture version and
45			configuration:
46	
47				# On uniprocessor ARM architectures previous to v7
48				  value must be 1, to enable a simple enumeration
49				  scheme for processors that do not have a HW CPU
50				  identification register.
51				# On 32-bit ARM 11 MPcore, ARM v7 or later systems
52				  value must be 1, that corresponds to CPUID/MPIDR
53				  registers sizes.
54				# On ARM v8 64-bit systems value should be set to 2,
55				  that corresponds to the MPIDR_EL1 register size.
56				  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57				  in the system, #address-cells can be set to 1, since
58				  MPIDR_EL1[63:32] bits are not used for CPUs
59				  identification.
60		- #size-cells
61			Usage: required
62			Value type: <u32>
63			Definition: must be set to 0
64	
65	- cpu node
66	
67		Description: Describes a CPU in an ARM based system
68	
69		PROPERTIES
70	
71		- device_type
72			Usage: required
73			Value type: <string>
74			Definition: must be "cpu"
75		- reg
76			Usage and definition depend on ARM architecture version and
77			configuration:
78	
79				# On uniprocessor ARM architectures previous to v7
80				  this property is required and must be set to 0.
81	
82				# On ARM 11 MPcore based systems this property is
83				  required and matches the CPUID[11:0] register bits.
84	
85				  Bits [11:0] in the reg cell must be set to
86				  bits [11:0] in CPU ID register.
87	
88				  All other bits in the reg cell must be set to 0.
89	
90				# On 32-bit ARM v7 or later systems this property is
91				  required and matches the CPU MPIDR[23:0] register
92				  bits.
93	
94				  Bits [23:0] in the reg cell must be set to
95				  bits [23:0] in MPIDR.
96	
97				  All other bits in the reg cell must be set to 0.
98	
99				# On ARM v8 64-bit systems this property is required
100				  and matches the MPIDR_EL1 register affinity bits.
101	
102				  * If cpus node's #address-cells property is set to 2
103	
104				    The first reg cell bits [7:0] must be set to
105				    bits [39:32] of MPIDR_EL1.
106	
107				    The second reg cell bits [23:0] must be set to
108				    bits [23:0] of MPIDR_EL1.
109	
110				  * If cpus node's #address-cells property is set to 1
111	
112				    The reg cell bits [23:0] must be set to bits [23:0]
113				    of MPIDR_EL1.
114	
115				  All other bits in the reg cells must be set to 0.
116	
117		- compatible:
118			Usage: required
119			Value type: <string>
120			Definition: should be one of:
121				    "arm,arm710t"
122				    "arm,arm720t"
123				    "arm,arm740t"
124				    "arm,arm7ej-s"
125				    "arm,arm7tdmi"
126				    "arm,arm7tdmi-s"
127				    "arm,arm9es"
128				    "arm,arm9ej-s"
129				    "arm,arm920t"
130				    "arm,arm922t"
131				    "arm,arm925"
132				    "arm,arm926e-s"
133				    "arm,arm926ej-s"
134				    "arm,arm940t"
135				    "arm,arm946e-s"
136				    "arm,arm966e-s"
137				    "arm,arm968e-s"
138				    "arm,arm9tdmi"
139				    "arm,arm1020e"
140				    "arm,arm1020t"
141				    "arm,arm1022e"
142				    "arm,arm1026ej-s"
143				    "arm,arm1136j-s"
144				    "arm,arm1136jf-s"
145				    "arm,arm1156t2-s"
146				    "arm,arm1156t2f-s"
147				    "arm,arm1176jzf"
148				    "arm,arm1176jz-s"
149				    "arm,arm1176jzf-s"
150				    "arm,arm11mpcore"
151				    "arm,cortex-a5"
152				    "arm,cortex-a7"
153				    "arm,cortex-a8"
154				    "arm,cortex-a9"
155				    "arm,cortex-a12"
156				    "arm,cortex-a15"
157				    "arm,cortex-a17"
158				    "arm,cortex-a53"
159				    "arm,cortex-a57"
160				    "arm,cortex-m0"
161				    "arm,cortex-m0+"
162				    "arm,cortex-m1"
163				    "arm,cortex-m3"
164				    "arm,cortex-m4"
165				    "arm,cortex-r4"
166				    "arm,cortex-r5"
167				    "arm,cortex-r7"
168				    "brcm,brahma-b15"
169				    "cavium,thunder"
170				    "faraday,fa526"
171				    "intel,sa110"
172				    "intel,sa1100"
173				    "marvell,feroceon"
174				    "marvell,mohawk"
175				    "marvell,pj4a"
176				    "marvell,pj4b"
177				    "marvell,sheeva-v5"
178				    "qcom,krait"
179				    "qcom,scorpion"
180		- enable-method
181			Value type: <stringlist>
182			Usage and definition depend on ARM architecture version.
183				# On ARM v8 64-bit this property is required and must
184				  be one of:
185				     "psci"
186				     "spin-table"
187				# On ARM 32-bit systems this property is optional and
188				  can be one of:
189				    "allwinner,sun6i-a31"
190				    "arm,psci"
191				    "brcm,brahma-b15"
192				    "marvell,armada-375-smp"
193				    "marvell,armada-380-smp"
194				    "marvell,armada-xp-smp"
195				    "qcom,gcc-msm8660"
196				    "qcom,kpss-acc-v1"
197				    "qcom,kpss-acc-v2"
198				    "rockchip,rk3066-smp"
199	
200		- cpu-release-addr
201			Usage: required for systems that have an "enable-method"
202			       property value of "spin-table".
203			Value type: <prop-encoded-array>
204			Definition:
205				# On ARM v8 64-bit systems must be a two cell
206				  property identifying a 64-bit zero-initialised
207				  memory location.
208	
209		- qcom,saw
210			Usage: required for systems that have an "enable-method"
211			       property value of "qcom,kpss-acc-v1" or
212			       "qcom,kpss-acc-v2"
213			Value type: <phandle>
214			Definition: Specifies the SAW[1] node associated with this CPU.
215	
216		- qcom,acc
217			Usage: required for systems that have an "enable-method"
218			       property value of "qcom,kpss-acc-v1" or
219			       "qcom,kpss-acc-v2"
220			Value type: <phandle>
221			Definition: Specifies the ACC[2] node associated with this CPU.
222	
223		- cpu-idle-states
224			Usage: Optional
225			Value type: <prop-encoded-array>
226			Definition:
227				# List of phandles to idle state nodes supported
228				  by this cpu [3].
229	
230		- rockchip,pmu
231			Usage: optional for systems that have an "enable-method"
232			       property value of "rockchip,rk3066-smp"
233			       While optional, it is the preferred way to get access to
234			       the cpu-core power-domains.
235			Value type: <phandle>
236			Definition: Specifies the syscon node controlling the cpu core
237				    power domains.
238	
239	Example 1 (dual-cluster big.LITTLE system 32-bit):
240	
241		cpus {
242			#size-cells = <0>;
243			#address-cells = <1>;
244	
245			cpu@0 {
246				device_type = "cpu";
247				compatible = "arm,cortex-a15";
248				reg = <0x0>;
249			};
250	
251			cpu@1 {
252				device_type = "cpu";
253				compatible = "arm,cortex-a15";
254				reg = <0x1>;
255			};
256	
257			cpu@100 {
258				device_type = "cpu";
259				compatible = "arm,cortex-a7";
260				reg = <0x100>;
261			};
262	
263			cpu@101 {
264				device_type = "cpu";
265				compatible = "arm,cortex-a7";
266				reg = <0x101>;
267			};
268		};
269	
270	Example 2 (Cortex-A8 uniprocessor 32-bit system):
271	
272		cpus {
273			#size-cells = <0>;
274			#address-cells = <1>;
275	
276			cpu@0 {
277				device_type = "cpu";
278				compatible = "arm,cortex-a8";
279				reg = <0x0>;
280			};
281		};
282	
283	Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
284	
285		cpus {
286			#size-cells = <0>;
287			#address-cells = <1>;
288	
289			cpu@0 {
290				device_type = "cpu";
291				compatible = "arm,arm926ej-s";
292				reg = <0x0>;
293			};
294		};
295	
296	Example 4 (ARM Cortex-A57 64-bit system):
297	
298	cpus {
299		#size-cells = <0>;
300		#address-cells = <2>;
301	
302		cpu@0 {
303			device_type = "cpu";
304			compatible = "arm,cortex-a57";
305			reg = <0x0 0x0>;
306			enable-method = "spin-table";
307			cpu-release-addr = <0 0x20000000>;
308		};
309	
310		cpu@1 {
311			device_type = "cpu";
312			compatible = "arm,cortex-a57";
313			reg = <0x0 0x1>;
314			enable-method = "spin-table";
315			cpu-release-addr = <0 0x20000000>;
316		};
317	
318		cpu@100 {
319			device_type = "cpu";
320			compatible = "arm,cortex-a57";
321			reg = <0x0 0x100>;
322			enable-method = "spin-table";
323			cpu-release-addr = <0 0x20000000>;
324		};
325	
326		cpu@101 {
327			device_type = "cpu";
328			compatible = "arm,cortex-a57";
329			reg = <0x0 0x101>;
330			enable-method = "spin-table";
331			cpu-release-addr = <0 0x20000000>;
332		};
333	
334		cpu@10000 {
335			device_type = "cpu";
336			compatible = "arm,cortex-a57";
337			reg = <0x0 0x10000>;
338			enable-method = "spin-table";
339			cpu-release-addr = <0 0x20000000>;
340		};
341	
342		cpu@10001 {
343			device_type = "cpu";
344			compatible = "arm,cortex-a57";
345			reg = <0x0 0x10001>;
346			enable-method = "spin-table";
347			cpu-release-addr = <0 0x20000000>;
348		};
349	
350		cpu@10100 {
351			device_type = "cpu";
352			compatible = "arm,cortex-a57";
353			reg = <0x0 0x10100>;
354			enable-method = "spin-table";
355			cpu-release-addr = <0 0x20000000>;
356		};
357	
358		cpu@10101 {
359			device_type = "cpu";
360			compatible = "arm,cortex-a57";
361			reg = <0x0 0x10101>;
362			enable-method = "spin-table";
363			cpu-release-addr = <0 0x20000000>;
364		};
365	
366		cpu@100000000 {
367			device_type = "cpu";
368			compatible = "arm,cortex-a57";
369			reg = <0x1 0x0>;
370			enable-method = "spin-table";
371			cpu-release-addr = <0 0x20000000>;
372		};
373	
374		cpu@100000001 {
375			device_type = "cpu";
376			compatible = "arm,cortex-a57";
377			reg = <0x1 0x1>;
378			enable-method = "spin-table";
379			cpu-release-addr = <0 0x20000000>;
380		};
381	
382		cpu@100000100 {
383			device_type = "cpu";
384			compatible = "arm,cortex-a57";
385			reg = <0x1 0x100>;
386			enable-method = "spin-table";
387			cpu-release-addr = <0 0x20000000>;
388		};
389	
390		cpu@100000101 {
391			device_type = "cpu";
392			compatible = "arm,cortex-a57";
393			reg = <0x1 0x101>;
394			enable-method = "spin-table";
395			cpu-release-addr = <0 0x20000000>;
396		};
397	
398		cpu@100010000 {
399			device_type = "cpu";
400			compatible = "arm,cortex-a57";
401			reg = <0x1 0x10000>;
402			enable-method = "spin-table";
403			cpu-release-addr = <0 0x20000000>;
404		};
405	
406		cpu@100010001 {
407			device_type = "cpu";
408			compatible = "arm,cortex-a57";
409			reg = <0x1 0x10001>;
410			enable-method = "spin-table";
411			cpu-release-addr = <0 0x20000000>;
412		};
413	
414		cpu@100010100 {
415			device_type = "cpu";
416			compatible = "arm,cortex-a57";
417			reg = <0x1 0x10100>;
418			enable-method = "spin-table";
419			cpu-release-addr = <0 0x20000000>;
420		};
421	
422		cpu@100010101 {
423			device_type = "cpu";
424			compatible = "arm,cortex-a57";
425			reg = <0x1 0x10101>;
426			enable-method = "spin-table";
427			cpu-release-addr = <0 0x20000000>;
428		};
429	};
430	
431	--
432	[1] arm/msm/qcom,saw2.txt
433	[2] arm/msm/qcom,kpss-acc.txt
434	[3] ARM Linux kernel documentation - idle states bindings
435	    Documentation/devicetree/bindings/arm/idle-states.txt
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