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Documentation / devicetree / bindings / arm / cpus.txt




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Based on kernel version 4.1. Page generated on 2015-06-28 12:08 EST.

1	=================
2	ARM CPUs bindings
3	=================
4	
5	The device tree allows to describe the layout of CPUs in a system through
6	the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7	defining properties for every cpu.
8	
9	Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
10	
11	https://www.power.org/documentation/epapr-version-1-1/
12	
13	with updates for 32-bit and 64-bit ARM systems provided in this document.
14	
15	================================
16	Convention used in this document
17	================================
18	
19	This document follows the conventions described in the ePAPR v1.1, with
20	the addition:
21	
22	- square brackets define bitfields, eg reg[7:0] value of the bitfield in
23	  the reg property contained in bits 7 down to 0
24	
25	=====================================
26	cpus and cpu node bindings definition
27	=====================================
28	
29	The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30	nodes to be present and contain the properties described below.
31	
32	- cpus node
33	
34		Description: Container of cpu nodes
35	
36		The node name must be "cpus".
37	
38		A cpus node must define the following properties:
39	
40		- #address-cells
41			Usage: required
42			Value type: <u32>
43	
44			Definition depends on ARM architecture version and
45			configuration:
46	
47				# On uniprocessor ARM architectures previous to v7
48				  value must be 1, to enable a simple enumeration
49				  scheme for processors that do not have a HW CPU
50				  identification register.
51				# On 32-bit ARM 11 MPcore, ARM v7 or later systems
52				  value must be 1, that corresponds to CPUID/MPIDR
53				  registers sizes.
54				# On ARM v8 64-bit systems value should be set to 2,
55				  that corresponds to the MPIDR_EL1 register size.
56				  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57				  in the system, #address-cells can be set to 1, since
58				  MPIDR_EL1[63:32] bits are not used for CPUs
59				  identification.
60		- #size-cells
61			Usage: required
62			Value type: <u32>
63			Definition: must be set to 0
64	
65	- cpu node
66	
67		Description: Describes a CPU in an ARM based system
68	
69		PROPERTIES
70	
71		- device_type
72			Usage: required
73			Value type: <string>
74			Definition: must be "cpu"
75		- reg
76			Usage and definition depend on ARM architecture version and
77			configuration:
78	
79				# On uniprocessor ARM architectures previous to v7
80				  this property is required and must be set to 0.
81	
82				# On ARM 11 MPcore based systems this property is
83				  required and matches the CPUID[11:0] register bits.
84	
85				  Bits [11:0] in the reg cell must be set to
86				  bits [11:0] in CPU ID register.
87	
88				  All other bits in the reg cell must be set to 0.
89	
90				# On 32-bit ARM v7 or later systems this property is
91				  required and matches the CPU MPIDR[23:0] register
92				  bits.
93	
94				  Bits [23:0] in the reg cell must be set to
95				  bits [23:0] in MPIDR.
96	
97				  All other bits in the reg cell must be set to 0.
98	
99				# On ARM v8 64-bit systems this property is required
100				  and matches the MPIDR_EL1 register affinity bits.
101	
102				  * If cpus node's #address-cells property is set to 2
103	
104				    The first reg cell bits [7:0] must be set to
105				    bits [39:32] of MPIDR_EL1.
106	
107				    The second reg cell bits [23:0] must be set to
108				    bits [23:0] of MPIDR_EL1.
109	
110				  * If cpus node's #address-cells property is set to 1
111	
112				    The reg cell bits [23:0] must be set to bits [23:0]
113				    of MPIDR_EL1.
114	
115				  All other bits in the reg cells must be set to 0.
116	
117		- compatible:
118			Usage: required
119			Value type: <string>
120			Definition: should be one of:
121				    "arm,arm710t"
122				    "arm,arm720t"
123				    "arm,arm740t"
124				    "arm,arm7ej-s"
125				    "arm,arm7tdmi"
126				    "arm,arm7tdmi-s"
127				    "arm,arm9es"
128				    "arm,arm9ej-s"
129				    "arm,arm920t"
130				    "arm,arm922t"
131				    "arm,arm925"
132				    "arm,arm926e-s"
133				    "arm,arm926ej-s"
134				    "arm,arm940t"
135				    "arm,arm946e-s"
136				    "arm,arm966e-s"
137				    "arm,arm968e-s"
138				    "arm,arm9tdmi"
139				    "arm,arm1020e"
140				    "arm,arm1020t"
141				    "arm,arm1022e"
142				    "arm,arm1026ej-s"
143				    "arm,arm1136j-s"
144				    "arm,arm1136jf-s"
145				    "arm,arm1156t2-s"
146				    "arm,arm1156t2f-s"
147				    "arm,arm1176jzf"
148				    "arm,arm1176jz-s"
149				    "arm,arm1176jzf-s"
150				    "arm,arm11mpcore"
151				    "arm,cortex-a5"
152				    "arm,cortex-a7"
153				    "arm,cortex-a8"
154				    "arm,cortex-a9"
155				    "arm,cortex-a12"
156				    "arm,cortex-a15"
157				    "arm,cortex-a17"
158				    "arm,cortex-a53"
159				    "arm,cortex-a57"
160				    "arm,cortex-m0"
161				    "arm,cortex-m0+"
162				    "arm,cortex-m1"
163				    "arm,cortex-m3"
164				    "arm,cortex-m4"
165				    "arm,cortex-r4"
166				    "arm,cortex-r5"
167				    "arm,cortex-r7"
168				    "brcm,brahma-b15"
169				    "cavium,thunder"
170				    "faraday,fa526"
171				    "intel,sa110"
172				    "intel,sa1100"
173				    "marvell,feroceon"
174				    "marvell,mohawk"
175				    "marvell,pj4a"
176				    "marvell,pj4b"
177				    "marvell,sheeva-v5"
178				    "nvidia,tegra132-denver"
179				    "qcom,krait"
180				    "qcom,scorpion"
181		- enable-method
182			Value type: <stringlist>
183			Usage and definition depend on ARM architecture version.
184				# On ARM v8 64-bit this property is required and must
185				  be one of:
186				     "psci"
187				     "spin-table"
188				# On ARM 32-bit systems this property is optional and
189				  can be one of:
190				    "allwinner,sun6i-a31"
191				    "arm,psci"
192				    "brcm,brahma-b15"
193				    "marvell,armada-375-smp"
194				    "marvell,armada-380-smp"
195				    "marvell,armada-390-smp"
196				    "marvell,armada-xp-smp"
197				    "qcom,gcc-msm8660"
198				    "qcom,kpss-acc-v1"
199				    "qcom,kpss-acc-v2"
200				    "rockchip,rk3066-smp"
201	
202		- cpu-release-addr
203			Usage: required for systems that have an "enable-method"
204			       property value of "spin-table".
205			Value type: <prop-encoded-array>
206			Definition:
207				# On ARM v8 64-bit systems must be a two cell
208				  property identifying a 64-bit zero-initialised
209				  memory location.
210	
211		- qcom,saw
212			Usage: required for systems that have an "enable-method"
213			       property value of "qcom,kpss-acc-v1" or
214			       "qcom,kpss-acc-v2"
215			Value type: <phandle>
216			Definition: Specifies the SAW[1] node associated with this CPU.
217	
218		- qcom,acc
219			Usage: required for systems that have an "enable-method"
220			       property value of "qcom,kpss-acc-v1" or
221			       "qcom,kpss-acc-v2"
222			Value type: <phandle>
223			Definition: Specifies the ACC[2] node associated with this CPU.
224	
225		- cpu-idle-states
226			Usage: Optional
227			Value type: <prop-encoded-array>
228			Definition:
229				# List of phandles to idle state nodes supported
230				  by this cpu [3].
231	
232		- rockchip,pmu
233			Usage: optional for systems that have an "enable-method"
234			       property value of "rockchip,rk3066-smp"
235			       While optional, it is the preferred way to get access to
236			       the cpu-core power-domains.
237			Value type: <phandle>
238			Definition: Specifies the syscon node controlling the cpu core
239				    power domains.
240	
241	Example 1 (dual-cluster big.LITTLE system 32-bit):
242	
243		cpus {
244			#size-cells = <0>;
245			#address-cells = <1>;
246	
247			cpu@0 {
248				device_type = "cpu";
249				compatible = "arm,cortex-a15";
250				reg = <0x0>;
251			};
252	
253			cpu@1 {
254				device_type = "cpu";
255				compatible = "arm,cortex-a15";
256				reg = <0x1>;
257			};
258	
259			cpu@100 {
260				device_type = "cpu";
261				compatible = "arm,cortex-a7";
262				reg = <0x100>;
263			};
264	
265			cpu@101 {
266				device_type = "cpu";
267				compatible = "arm,cortex-a7";
268				reg = <0x101>;
269			};
270		};
271	
272	Example 2 (Cortex-A8 uniprocessor 32-bit system):
273	
274		cpus {
275			#size-cells = <0>;
276			#address-cells = <1>;
277	
278			cpu@0 {
279				device_type = "cpu";
280				compatible = "arm,cortex-a8";
281				reg = <0x0>;
282			};
283		};
284	
285	Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
286	
287		cpus {
288			#size-cells = <0>;
289			#address-cells = <1>;
290	
291			cpu@0 {
292				device_type = "cpu";
293				compatible = "arm,arm926ej-s";
294				reg = <0x0>;
295			};
296		};
297	
298	Example 4 (ARM Cortex-A57 64-bit system):
299	
300	cpus {
301		#size-cells = <0>;
302		#address-cells = <2>;
303	
304		cpu@0 {
305			device_type = "cpu";
306			compatible = "arm,cortex-a57";
307			reg = <0x0 0x0>;
308			enable-method = "spin-table";
309			cpu-release-addr = <0 0x20000000>;
310		};
311	
312		cpu@1 {
313			device_type = "cpu";
314			compatible = "arm,cortex-a57";
315			reg = <0x0 0x1>;
316			enable-method = "spin-table";
317			cpu-release-addr = <0 0x20000000>;
318		};
319	
320		cpu@100 {
321			device_type = "cpu";
322			compatible = "arm,cortex-a57";
323			reg = <0x0 0x100>;
324			enable-method = "spin-table";
325			cpu-release-addr = <0 0x20000000>;
326		};
327	
328		cpu@101 {
329			device_type = "cpu";
330			compatible = "arm,cortex-a57";
331			reg = <0x0 0x101>;
332			enable-method = "spin-table";
333			cpu-release-addr = <0 0x20000000>;
334		};
335	
336		cpu@10000 {
337			device_type = "cpu";
338			compatible = "arm,cortex-a57";
339			reg = <0x0 0x10000>;
340			enable-method = "spin-table";
341			cpu-release-addr = <0 0x20000000>;
342		};
343	
344		cpu@10001 {
345			device_type = "cpu";
346			compatible = "arm,cortex-a57";
347			reg = <0x0 0x10001>;
348			enable-method = "spin-table";
349			cpu-release-addr = <0 0x20000000>;
350		};
351	
352		cpu@10100 {
353			device_type = "cpu";
354			compatible = "arm,cortex-a57";
355			reg = <0x0 0x10100>;
356			enable-method = "spin-table";
357			cpu-release-addr = <0 0x20000000>;
358		};
359	
360		cpu@10101 {
361			device_type = "cpu";
362			compatible = "arm,cortex-a57";
363			reg = <0x0 0x10101>;
364			enable-method = "spin-table";
365			cpu-release-addr = <0 0x20000000>;
366		};
367	
368		cpu@100000000 {
369			device_type = "cpu";
370			compatible = "arm,cortex-a57";
371			reg = <0x1 0x0>;
372			enable-method = "spin-table";
373			cpu-release-addr = <0 0x20000000>;
374		};
375	
376		cpu@100000001 {
377			device_type = "cpu";
378			compatible = "arm,cortex-a57";
379			reg = <0x1 0x1>;
380			enable-method = "spin-table";
381			cpu-release-addr = <0 0x20000000>;
382		};
383	
384		cpu@100000100 {
385			device_type = "cpu";
386			compatible = "arm,cortex-a57";
387			reg = <0x1 0x100>;
388			enable-method = "spin-table";
389			cpu-release-addr = <0 0x20000000>;
390		};
391	
392		cpu@100000101 {
393			device_type = "cpu";
394			compatible = "arm,cortex-a57";
395			reg = <0x1 0x101>;
396			enable-method = "spin-table";
397			cpu-release-addr = <0 0x20000000>;
398		};
399	
400		cpu@100010000 {
401			device_type = "cpu";
402			compatible = "arm,cortex-a57";
403			reg = <0x1 0x10000>;
404			enable-method = "spin-table";
405			cpu-release-addr = <0 0x20000000>;
406		};
407	
408		cpu@100010001 {
409			device_type = "cpu";
410			compatible = "arm,cortex-a57";
411			reg = <0x1 0x10001>;
412			enable-method = "spin-table";
413			cpu-release-addr = <0 0x20000000>;
414		};
415	
416		cpu@100010100 {
417			device_type = "cpu";
418			compatible = "arm,cortex-a57";
419			reg = <0x1 0x10100>;
420			enable-method = "spin-table";
421			cpu-release-addr = <0 0x20000000>;
422		};
423	
424		cpu@100010101 {
425			device_type = "cpu";
426			compatible = "arm,cortex-a57";
427			reg = <0x1 0x10101>;
428			enable-method = "spin-table";
429			cpu-release-addr = <0 0x20000000>;
430		};
431	};
432	
433	--
434	[1] arm/msm/qcom,saw2.txt
435	[2] arm/msm/qcom,kpss-acc.txt
436	[3] ARM Linux kernel documentation - idle states bindings
437	    Documentation/devicetree/bindings/arm/idle-states.txt
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