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Documentation / devicetree / bindings / arm / cpus.txt




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Based on kernel version 3.13. Page generated on 2014-01-20 22:00 EST.

1	=================
2	ARM CPUs bindings
3	=================
4	
5	The device tree allows to describe the layout of CPUs in a system through
6	the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7	defining properties for every cpu.
8	
9	Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
10	
11	https://www.power.org/documentation/epapr-version-1-1/
12	
13	with updates for 32-bit and 64-bit ARM systems provided in this document.
14	
15	================================
16	Convention used in this document
17	================================
18	
19	This document follows the conventions described in the ePAPR v1.1, with
20	the addition:
21	
22	- square brackets define bitfields, eg reg[7:0] value of the bitfield in
23	  the reg property contained in bits 7 down to 0
24	
25	=====================================
26	cpus and cpu node bindings definition
27	=====================================
28	
29	The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30	nodes to be present and contain the properties described below.
31	
32	- cpus node
33	
34		Description: Container of cpu nodes
35	
36		The node name must be "cpus".
37	
38		A cpus node must define the following properties:
39	
40		- #address-cells
41			Usage: required
42			Value type: <u32>
43	
44			Definition depends on ARM architecture version and
45			configuration:
46	
47				# On uniprocessor ARM architectures previous to v7
48				  value must be 1, to enable a simple enumeration
49				  scheme for processors that do not have a HW CPU
50				  identification register.
51				# On 32-bit ARM 11 MPcore, ARM v7 or later systems
52				  value must be 1, that corresponds to CPUID/MPIDR
53				  registers sizes.
54				# On ARM v8 64-bit systems value should be set to 2,
55				  that corresponds to the MPIDR_EL1 register size.
56				  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57				  in the system, #address-cells can be set to 1, since
58				  MPIDR_EL1[63:32] bits are not used for CPUs
59				  identification.
60		- #size-cells
61			Usage: required
62			Value type: <u32>
63			Definition: must be set to 0
64	
65	- cpu node
66	
67		Description: Describes a CPU in an ARM based system
68	
69		PROPERTIES
70	
71		- device_type
72			Usage: required
73			Value type: <string>
74			Definition: must be "cpu"
75		- reg
76			Usage and definition depend on ARM architecture version and
77			configuration:
78	
79				# On uniprocessor ARM architectures previous to v7
80				  this property is required and must be set to 0.
81	
82				# On ARM 11 MPcore based systems this property is
83				  required and matches the CPUID[11:0] register bits.
84	
85				  Bits [11:0] in the reg cell must be set to
86				  bits [11:0] in CPU ID register.
87	
88				  All other bits in the reg cell must be set to 0.
89	
90				# On 32-bit ARM v7 or later systems this property is
91				  required and matches the CPU MPIDR[23:0] register
92				  bits.
93	
94				  Bits [23:0] in the reg cell must be set to
95				  bits [23:0] in MPIDR.
96	
97				  All other bits in the reg cell must be set to 0.
98	
99				# On ARM v8 64-bit systems this property is required
100				  and matches the MPIDR_EL1 register affinity bits.
101	
102				  * If cpus node's #address-cells property is set to 2
103	
104				    The first reg cell bits [7:0] must be set to
105				    bits [39:32] of MPIDR_EL1.
106	
107				    The second reg cell bits [23:0] must be set to
108				    bits [23:0] of MPIDR_EL1.
109	
110				  * If cpus node's #address-cells property is set to 1
111	
112				    The reg cell bits [23:0] must be set to bits [23:0]
113				    of MPIDR_EL1.
114	
115				  All other bits in the reg cells must be set to 0.
116	
117		- compatible:
118			Usage: required
119			Value type: <string>
120			Definition: should be one of:
121				    "arm,arm710t"
122				    "arm,arm720t"
123				    "arm,arm740t"
124				    "arm,arm7ej-s"
125				    "arm,arm7tdmi"
126				    "arm,arm7tdmi-s"
127				    "arm,arm9es"
128				    "arm,arm9ej-s"
129				    "arm,arm920t"
130				    "arm,arm922t"
131				    "arm,arm925"
132				    "arm,arm926e-s"
133				    "arm,arm926ej-s"
134				    "arm,arm940t"
135				    "arm,arm946e-s"
136				    "arm,arm966e-s"
137				    "arm,arm968e-s"
138				    "arm,arm9tdmi"
139				    "arm,arm1020e"
140				    "arm,arm1020t"
141				    "arm,arm1022e"
142				    "arm,arm1026ej-s"
143				    "arm,arm1136j-s"
144				    "arm,arm1136jf-s"
145				    "arm,arm1156t2-s"
146				    "arm,arm1156t2f-s"
147				    "arm,arm1176jzf"
148				    "arm,arm1176jz-s"
149				    "arm,arm1176jzf-s"
150				    "arm,arm11mpcore"
151				    "arm,cortex-a5"
152				    "arm,cortex-a7"
153				    "arm,cortex-a8"
154				    "arm,cortex-a9"
155				    "arm,cortex-a15"
156				    "arm,cortex-a53"
157				    "arm,cortex-a57"
158				    "arm,cortex-m0"
159				    "arm,cortex-m0+"
160				    "arm,cortex-m1"
161				    "arm,cortex-m3"
162				    "arm,cortex-m4"
163				    "arm,cortex-r4"
164				    "arm,cortex-r5"
165				    "arm,cortex-r7"
166				    "faraday,fa526"
167				    "intel,sa110"
168				    "intel,sa1100"
169				    "marvell,feroceon"
170				    "marvell,mohawk"
171				    "marvell,pj4a"
172				    "marvell,pj4b"
173				    "marvell,sheeva-v5"
174				    "qcom,krait"
175				    "qcom,scorpion"
176		- enable-method
177			Value type: <stringlist>
178			Usage and definition depend on ARM architecture version.
179				# On ARM v8 64-bit this property is required and must
180				  be one of:
181				     "spin-table"
182				     "psci"
183				# On ARM 32-bit systems this property is optional.
184	
185		- cpu-release-addr
186			Usage: required for systems that have an "enable-method"
187			       property value of "spin-table".
188			Value type: <prop-encoded-array>
189			Definition:
190				# On ARM v8 64-bit systems must be a two cell
191				  property identifying a 64-bit zero-initialised
192				  memory location.
193	
194	Example 1 (dual-cluster big.LITTLE system 32-bit):
195	
196		cpus {
197			#size-cells = <0>;
198			#address-cells = <1>;
199	
200			cpu@0 {
201				device_type = "cpu";
202				compatible = "arm,cortex-a15";
203				reg = <0x0>;
204			};
205	
206			cpu@1 {
207				device_type = "cpu";
208				compatible = "arm,cortex-a15";
209				reg = <0x1>;
210			};
211	
212			cpu@100 {
213				device_type = "cpu";
214				compatible = "arm,cortex-a7";
215				reg = <0x100>;
216			};
217	
218			cpu@101 {
219				device_type = "cpu";
220				compatible = "arm,cortex-a7";
221				reg = <0x101>;
222			};
223		};
224	
225	Example 2 (Cortex-A8 uniprocessor 32-bit system):
226	
227		cpus {
228			#size-cells = <0>;
229			#address-cells = <1>;
230	
231			cpu@0 {
232				device_type = "cpu";
233				compatible = "arm,cortex-a8";
234				reg = <0x0>;
235			};
236		};
237	
238	Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
239	
240		cpus {
241			#size-cells = <0>;
242			#address-cells = <1>;
243	
244			cpu@0 {
245				device_type = "cpu";
246				compatible = "arm,arm926ej-s";
247				reg = <0x0>;
248			};
249		};
250	
251	Example 4 (ARM Cortex-A57 64-bit system):
252	
253	cpus {
254		#size-cells = <0>;
255		#address-cells = <2>;
256	
257		cpu@0 {
258			device_type = "cpu";
259			compatible = "arm,cortex-a57";
260			reg = <0x0 0x0>;
261			enable-method = "spin-table";
262			cpu-release-addr = <0 0x20000000>;
263		};
264	
265		cpu@1 {
266			device_type = "cpu";
267			compatible = "arm,cortex-a57";
268			reg = <0x0 0x1>;
269			enable-method = "spin-table";
270			cpu-release-addr = <0 0x20000000>;
271		};
272	
273		cpu@100 {
274			device_type = "cpu";
275			compatible = "arm,cortex-a57";
276			reg = <0x0 0x100>;
277			enable-method = "spin-table";
278			cpu-release-addr = <0 0x20000000>;
279		};
280	
281		cpu@101 {
282			device_type = "cpu";
283			compatible = "arm,cortex-a57";
284			reg = <0x0 0x101>;
285			enable-method = "spin-table";
286			cpu-release-addr = <0 0x20000000>;
287		};
288	
289		cpu@10000 {
290			device_type = "cpu";
291			compatible = "arm,cortex-a57";
292			reg = <0x0 0x10000>;
293			enable-method = "spin-table";
294			cpu-release-addr = <0 0x20000000>;
295		};
296	
297		cpu@10001 {
298			device_type = "cpu";
299			compatible = "arm,cortex-a57";
300			reg = <0x0 0x10001>;
301			enable-method = "spin-table";
302			cpu-release-addr = <0 0x20000000>;
303		};
304	
305		cpu@10100 {
306			device_type = "cpu";
307			compatible = "arm,cortex-a57";
308			reg = <0x0 0x10100>;
309			enable-method = "spin-table";
310			cpu-release-addr = <0 0x20000000>;
311		};
312	
313		cpu@10101 {
314			device_type = "cpu";
315			compatible = "arm,cortex-a57";
316			reg = <0x0 0x10101>;
317			enable-method = "spin-table";
318			cpu-release-addr = <0 0x20000000>;
319		};
320	
321		cpu@100000000 {
322			device_type = "cpu";
323			compatible = "arm,cortex-a57";
324			reg = <0x1 0x0>;
325			enable-method = "spin-table";
326			cpu-release-addr = <0 0x20000000>;
327		};
328	
329		cpu@100000001 {
330			device_type = "cpu";
331			compatible = "arm,cortex-a57";
332			reg = <0x1 0x1>;
333			enable-method = "spin-table";
334			cpu-release-addr = <0 0x20000000>;
335		};
336	
337		cpu@100000100 {
338			device_type = "cpu";
339			compatible = "arm,cortex-a57";
340			reg = <0x1 0x100>;
341			enable-method = "spin-table";
342			cpu-release-addr = <0 0x20000000>;
343		};
344	
345		cpu@100000101 {
346			device_type = "cpu";
347			compatible = "arm,cortex-a57";
348			reg = <0x1 0x101>;
349			enable-method = "spin-table";
350			cpu-release-addr = <0 0x20000000>;
351		};
352	
353		cpu@100010000 {
354			device_type = "cpu";
355			compatible = "arm,cortex-a57";
356			reg = <0x1 0x10000>;
357			enable-method = "spin-table";
358			cpu-release-addr = <0 0x20000000>;
359		};
360	
361		cpu@100010001 {
362			device_type = "cpu";
363			compatible = "arm,cortex-a57";
364			reg = <0x1 0x10001>;
365			enable-method = "spin-table";
366			cpu-release-addr = <0 0x20000000>;
367		};
368	
369		cpu@100010100 {
370			device_type = "cpu";
371			compatible = "arm,cortex-a57";
372			reg = <0x1 0x10100>;
373			enable-method = "spin-table";
374			cpu-release-addr = <0 0x20000000>;
375		};
376	
377		cpu@100010101 {
378			device_type = "cpu";
379			compatible = "arm,cortex-a57";
380			reg = <0x1 0x10101>;
381			enable-method = "spin-table";
382			cpu-release-addr = <0 0x20000000>;
383		};
384	};
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