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Documentation / devicetree / bindings / arm / cpus.txt




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Based on kernel version 4.0. Page generated on 2015-04-14 21:20 EST.

1	=================
2	ARM CPUs bindings
3	=================
4	
5	The device tree allows to describe the layout of CPUs in a system through
6	the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7	defining properties for every cpu.
8	
9	Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
10	
11	https://www.power.org/documentation/epapr-version-1-1/
12	
13	with updates for 32-bit and 64-bit ARM systems provided in this document.
14	
15	================================
16	Convention used in this document
17	================================
18	
19	This document follows the conventions described in the ePAPR v1.1, with
20	the addition:
21	
22	- square brackets define bitfields, eg reg[7:0] value of the bitfield in
23	  the reg property contained in bits 7 down to 0
24	
25	=====================================
26	cpus and cpu node bindings definition
27	=====================================
28	
29	The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30	nodes to be present and contain the properties described below.
31	
32	- cpus node
33	
34		Description: Container of cpu nodes
35	
36		The node name must be "cpus".
37	
38		A cpus node must define the following properties:
39	
40		- #address-cells
41			Usage: required
42			Value type: <u32>
43	
44			Definition depends on ARM architecture version and
45			configuration:
46	
47				# On uniprocessor ARM architectures previous to v7
48				  value must be 1, to enable a simple enumeration
49				  scheme for processors that do not have a HW CPU
50				  identification register.
51				# On 32-bit ARM 11 MPcore, ARM v7 or later systems
52				  value must be 1, that corresponds to CPUID/MPIDR
53				  registers sizes.
54				# On ARM v8 64-bit systems value should be set to 2,
55				  that corresponds to the MPIDR_EL1 register size.
56				  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57				  in the system, #address-cells can be set to 1, since
58				  MPIDR_EL1[63:32] bits are not used for CPUs
59				  identification.
60		- #size-cells
61			Usage: required
62			Value type: <u32>
63			Definition: must be set to 0
64	
65	- cpu node
66	
67		Description: Describes a CPU in an ARM based system
68	
69		PROPERTIES
70	
71		- device_type
72			Usage: required
73			Value type: <string>
74			Definition: must be "cpu"
75		- reg
76			Usage and definition depend on ARM architecture version and
77			configuration:
78	
79				# On uniprocessor ARM architectures previous to v7
80				  this property is required and must be set to 0.
81	
82				# On ARM 11 MPcore based systems this property is
83				  required and matches the CPUID[11:0] register bits.
84	
85				  Bits [11:0] in the reg cell must be set to
86				  bits [11:0] in CPU ID register.
87	
88				  All other bits in the reg cell must be set to 0.
89	
90				# On 32-bit ARM v7 or later systems this property is
91				  required and matches the CPU MPIDR[23:0] register
92				  bits.
93	
94				  Bits [23:0] in the reg cell must be set to
95				  bits [23:0] in MPIDR.
96	
97				  All other bits in the reg cell must be set to 0.
98	
99				# On ARM v8 64-bit systems this property is required
100				  and matches the MPIDR_EL1 register affinity bits.
101	
102				  * If cpus node's #address-cells property is set to 2
103	
104				    The first reg cell bits [7:0] must be set to
105				    bits [39:32] of MPIDR_EL1.
106	
107				    The second reg cell bits [23:0] must be set to
108				    bits [23:0] of MPIDR_EL1.
109	
110				  * If cpus node's #address-cells property is set to 1
111	
112				    The reg cell bits [23:0] must be set to bits [23:0]
113				    of MPIDR_EL1.
114	
115				  All other bits in the reg cells must be set to 0.
116	
117		- compatible:
118			Usage: required
119			Value type: <string>
120			Definition: should be one of:
121				    "arm,arm710t"
122				    "arm,arm720t"
123				    "arm,arm740t"
124				    "arm,arm7ej-s"
125				    "arm,arm7tdmi"
126				    "arm,arm7tdmi-s"
127				    "arm,arm9es"
128				    "arm,arm9ej-s"
129				    "arm,arm920t"
130				    "arm,arm922t"
131				    "arm,arm925"
132				    "arm,arm926e-s"
133				    "arm,arm926ej-s"
134				    "arm,arm940t"
135				    "arm,arm946e-s"
136				    "arm,arm966e-s"
137				    "arm,arm968e-s"
138				    "arm,arm9tdmi"
139				    "arm,arm1020e"
140				    "arm,arm1020t"
141				    "arm,arm1022e"
142				    "arm,arm1026ej-s"
143				    "arm,arm1136j-s"
144				    "arm,arm1136jf-s"
145				    "arm,arm1156t2-s"
146				    "arm,arm1156t2f-s"
147				    "arm,arm1176jzf"
148				    "arm,arm1176jz-s"
149				    "arm,arm1176jzf-s"
150				    "arm,arm11mpcore"
151				    "arm,cortex-a5"
152				    "arm,cortex-a7"
153				    "arm,cortex-a8"
154				    "arm,cortex-a9"
155				    "arm,cortex-a12"
156				    "arm,cortex-a15"
157				    "arm,cortex-a17"
158				    "arm,cortex-a53"
159				    "arm,cortex-a57"
160				    "arm,cortex-m0"
161				    "arm,cortex-m0+"
162				    "arm,cortex-m1"
163				    "arm,cortex-m3"
164				    "arm,cortex-m4"
165				    "arm,cortex-r4"
166				    "arm,cortex-r5"
167				    "arm,cortex-r7"
168				    "brcm,brahma-b15"
169				    "cavium,thunder"
170				    "faraday,fa526"
171				    "intel,sa110"
172				    "intel,sa1100"
173				    "marvell,feroceon"
174				    "marvell,mohawk"
175				    "marvell,pj4a"
176				    "marvell,pj4b"
177				    "marvell,sheeva-v5"
178				    "nvidia,tegra132-denver"
179				    "qcom,krait"
180				    "qcom,scorpion"
181		- enable-method
182			Value type: <stringlist>
183			Usage and definition depend on ARM architecture version.
184				# On ARM v8 64-bit this property is required and must
185				  be one of:
186				     "psci"
187				     "spin-table"
188				# On ARM 32-bit systems this property is optional and
189				  can be one of:
190				    "allwinner,sun6i-a31"
191				    "arm,psci"
192				    "brcm,brahma-b15"
193				    "marvell,armada-375-smp"
194				    "marvell,armada-380-smp"
195				    "marvell,armada-xp-smp"
196				    "qcom,gcc-msm8660"
197				    "qcom,kpss-acc-v1"
198				    "qcom,kpss-acc-v2"
199				    "rockchip,rk3066-smp"
200	
201		- cpu-release-addr
202			Usage: required for systems that have an "enable-method"
203			       property value of "spin-table".
204			Value type: <prop-encoded-array>
205			Definition:
206				# On ARM v8 64-bit systems must be a two cell
207				  property identifying a 64-bit zero-initialised
208				  memory location.
209	
210		- qcom,saw
211			Usage: required for systems that have an "enable-method"
212			       property value of "qcom,kpss-acc-v1" or
213			       "qcom,kpss-acc-v2"
214			Value type: <phandle>
215			Definition: Specifies the SAW[1] node associated with this CPU.
216	
217		- qcom,acc
218			Usage: required for systems that have an "enable-method"
219			       property value of "qcom,kpss-acc-v1" or
220			       "qcom,kpss-acc-v2"
221			Value type: <phandle>
222			Definition: Specifies the ACC[2] node associated with this CPU.
223	
224		- cpu-idle-states
225			Usage: Optional
226			Value type: <prop-encoded-array>
227			Definition:
228				# List of phandles to idle state nodes supported
229				  by this cpu [3].
230	
231		- rockchip,pmu
232			Usage: optional for systems that have an "enable-method"
233			       property value of "rockchip,rk3066-smp"
234			       While optional, it is the preferred way to get access to
235			       the cpu-core power-domains.
236			Value type: <phandle>
237			Definition: Specifies the syscon node controlling the cpu core
238				    power domains.
239	
240	Example 1 (dual-cluster big.LITTLE system 32-bit):
241	
242		cpus {
243			#size-cells = <0>;
244			#address-cells = <1>;
245	
246			cpu@0 {
247				device_type = "cpu";
248				compatible = "arm,cortex-a15";
249				reg = <0x0>;
250			};
251	
252			cpu@1 {
253				device_type = "cpu";
254				compatible = "arm,cortex-a15";
255				reg = <0x1>;
256			};
257	
258			cpu@100 {
259				device_type = "cpu";
260				compatible = "arm,cortex-a7";
261				reg = <0x100>;
262			};
263	
264			cpu@101 {
265				device_type = "cpu";
266				compatible = "arm,cortex-a7";
267				reg = <0x101>;
268			};
269		};
270	
271	Example 2 (Cortex-A8 uniprocessor 32-bit system):
272	
273		cpus {
274			#size-cells = <0>;
275			#address-cells = <1>;
276	
277			cpu@0 {
278				device_type = "cpu";
279				compatible = "arm,cortex-a8";
280				reg = <0x0>;
281			};
282		};
283	
284	Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
285	
286		cpus {
287			#size-cells = <0>;
288			#address-cells = <1>;
289	
290			cpu@0 {
291				device_type = "cpu";
292				compatible = "arm,arm926ej-s";
293				reg = <0x0>;
294			};
295		};
296	
297	Example 4 (ARM Cortex-A57 64-bit system):
298	
299	cpus {
300		#size-cells = <0>;
301		#address-cells = <2>;
302	
303		cpu@0 {
304			device_type = "cpu";
305			compatible = "arm,cortex-a57";
306			reg = <0x0 0x0>;
307			enable-method = "spin-table";
308			cpu-release-addr = <0 0x20000000>;
309		};
310	
311		cpu@1 {
312			device_type = "cpu";
313			compatible = "arm,cortex-a57";
314			reg = <0x0 0x1>;
315			enable-method = "spin-table";
316			cpu-release-addr = <0 0x20000000>;
317		};
318	
319		cpu@100 {
320			device_type = "cpu";
321			compatible = "arm,cortex-a57";
322			reg = <0x0 0x100>;
323			enable-method = "spin-table";
324			cpu-release-addr = <0 0x20000000>;
325		};
326	
327		cpu@101 {
328			device_type = "cpu";
329			compatible = "arm,cortex-a57";
330			reg = <0x0 0x101>;
331			enable-method = "spin-table";
332			cpu-release-addr = <0 0x20000000>;
333		};
334	
335		cpu@10000 {
336			device_type = "cpu";
337			compatible = "arm,cortex-a57";
338			reg = <0x0 0x10000>;
339			enable-method = "spin-table";
340			cpu-release-addr = <0 0x20000000>;
341		};
342	
343		cpu@10001 {
344			device_type = "cpu";
345			compatible = "arm,cortex-a57";
346			reg = <0x0 0x10001>;
347			enable-method = "spin-table";
348			cpu-release-addr = <0 0x20000000>;
349		};
350	
351		cpu@10100 {
352			device_type = "cpu";
353			compatible = "arm,cortex-a57";
354			reg = <0x0 0x10100>;
355			enable-method = "spin-table";
356			cpu-release-addr = <0 0x20000000>;
357		};
358	
359		cpu@10101 {
360			device_type = "cpu";
361			compatible = "arm,cortex-a57";
362			reg = <0x0 0x10101>;
363			enable-method = "spin-table";
364			cpu-release-addr = <0 0x20000000>;
365		};
366	
367		cpu@100000000 {
368			device_type = "cpu";
369			compatible = "arm,cortex-a57";
370			reg = <0x1 0x0>;
371			enable-method = "spin-table";
372			cpu-release-addr = <0 0x20000000>;
373		};
374	
375		cpu@100000001 {
376			device_type = "cpu";
377			compatible = "arm,cortex-a57";
378			reg = <0x1 0x1>;
379			enable-method = "spin-table";
380			cpu-release-addr = <0 0x20000000>;
381		};
382	
383		cpu@100000100 {
384			device_type = "cpu";
385			compatible = "arm,cortex-a57";
386			reg = <0x1 0x100>;
387			enable-method = "spin-table";
388			cpu-release-addr = <0 0x20000000>;
389		};
390	
391		cpu@100000101 {
392			device_type = "cpu";
393			compatible = "arm,cortex-a57";
394			reg = <0x1 0x101>;
395			enable-method = "spin-table";
396			cpu-release-addr = <0 0x20000000>;
397		};
398	
399		cpu@100010000 {
400			device_type = "cpu";
401			compatible = "arm,cortex-a57";
402			reg = <0x1 0x10000>;
403			enable-method = "spin-table";
404			cpu-release-addr = <0 0x20000000>;
405		};
406	
407		cpu@100010001 {
408			device_type = "cpu";
409			compatible = "arm,cortex-a57";
410			reg = <0x1 0x10001>;
411			enable-method = "spin-table";
412			cpu-release-addr = <0 0x20000000>;
413		};
414	
415		cpu@100010100 {
416			device_type = "cpu";
417			compatible = "arm,cortex-a57";
418			reg = <0x1 0x10100>;
419			enable-method = "spin-table";
420			cpu-release-addr = <0 0x20000000>;
421		};
422	
423		cpu@100010101 {
424			device_type = "cpu";
425			compatible = "arm,cortex-a57";
426			reg = <0x1 0x10101>;
427			enable-method = "spin-table";
428			cpu-release-addr = <0 0x20000000>;
429		};
430	};
431	
432	--
433	[1] arm/msm/qcom,saw2.txt
434	[2] arm/msm/qcom,kpss-acc.txt
435	[3] ARM Linux kernel documentation - idle states bindings
436	    Documentation/devicetree/bindings/arm/idle-states.txt
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