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Documentation / devicetree / bindings / arm / cpus.txt




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Based on kernel version 4.3. Page generated on 2015-11-02 12:44 EST.

1	=================
2	ARM CPUs bindings
3	=================
4	
5	The device tree allows to describe the layout of CPUs in a system through
6	the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7	defining properties for every cpu.
8	
9	Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
10	
11	https://www.power.org/documentation/epapr-version-1-1/
12	
13	with updates for 32-bit and 64-bit ARM systems provided in this document.
14	
15	================================
16	Convention used in this document
17	================================
18	
19	This document follows the conventions described in the ePAPR v1.1, with
20	the addition:
21	
22	- square brackets define bitfields, eg reg[7:0] value of the bitfield in
23	  the reg property contained in bits 7 down to 0
24	
25	=====================================
26	cpus and cpu node bindings definition
27	=====================================
28	
29	The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30	nodes to be present and contain the properties described below.
31	
32	- cpus node
33	
34		Description: Container of cpu nodes
35	
36		The node name must be "cpus".
37	
38		A cpus node must define the following properties:
39	
40		- #address-cells
41			Usage: required
42			Value type: <u32>
43	
44			Definition depends on ARM architecture version and
45			configuration:
46	
47				# On uniprocessor ARM architectures previous to v7
48				  value must be 1, to enable a simple enumeration
49				  scheme for processors that do not have a HW CPU
50				  identification register.
51				# On 32-bit ARM 11 MPcore, ARM v7 or later systems
52				  value must be 1, that corresponds to CPUID/MPIDR
53				  registers sizes.
54				# On ARM v8 64-bit systems value should be set to 2,
55				  that corresponds to the MPIDR_EL1 register size.
56				  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57				  in the system, #address-cells can be set to 1, since
58				  MPIDR_EL1[63:32] bits are not used for CPUs
59				  identification.
60		- #size-cells
61			Usage: required
62			Value type: <u32>
63			Definition: must be set to 0
64	
65	- cpu node
66	
67		Description: Describes a CPU in an ARM based system
68	
69		PROPERTIES
70	
71		- device_type
72			Usage: required
73			Value type: <string>
74			Definition: must be "cpu"
75		- reg
76			Usage and definition depend on ARM architecture version and
77			configuration:
78	
79				# On uniprocessor ARM architectures previous to v7
80				  this property is required and must be set to 0.
81	
82				# On ARM 11 MPcore based systems this property is
83				  required and matches the CPUID[11:0] register bits.
84	
85				  Bits [11:0] in the reg cell must be set to
86				  bits [11:0] in CPU ID register.
87	
88				  All other bits in the reg cell must be set to 0.
89	
90				# On 32-bit ARM v7 or later systems this property is
91				  required and matches the CPU MPIDR[23:0] register
92				  bits.
93	
94				  Bits [23:0] in the reg cell must be set to
95				  bits [23:0] in MPIDR.
96	
97				  All other bits in the reg cell must be set to 0.
98	
99				# On ARM v8 64-bit systems this property is required
100				  and matches the MPIDR_EL1 register affinity bits.
101	
102				  * If cpus node's #address-cells property is set to 2
103	
104				    The first reg cell bits [7:0] must be set to
105				    bits [39:32] of MPIDR_EL1.
106	
107				    The second reg cell bits [23:0] must be set to
108				    bits [23:0] of MPIDR_EL1.
109	
110				  * If cpus node's #address-cells property is set to 1
111	
112				    The reg cell bits [23:0] must be set to bits [23:0]
113				    of MPIDR_EL1.
114	
115				  All other bits in the reg cells must be set to 0.
116	
117		- compatible:
118			Usage: required
119			Value type: <string>
120			Definition: should be one of:
121				    "arm,arm710t"
122				    "arm,arm720t"
123				    "arm,arm740t"
124				    "arm,arm7ej-s"
125				    "arm,arm7tdmi"
126				    "arm,arm7tdmi-s"
127				    "arm,arm9es"
128				    "arm,arm9ej-s"
129				    "arm,arm920t"
130				    "arm,arm922t"
131				    "arm,arm925"
132				    "arm,arm926e-s"
133				    "arm,arm926ej-s"
134				    "arm,arm940t"
135				    "arm,arm946e-s"
136				    "arm,arm966e-s"
137				    "arm,arm968e-s"
138				    "arm,arm9tdmi"
139				    "arm,arm1020e"
140				    "arm,arm1020t"
141				    "arm,arm1022e"
142				    "arm,arm1026ej-s"
143				    "arm,arm1136j-s"
144				    "arm,arm1136jf-s"
145				    "arm,arm1156t2-s"
146				    "arm,arm1156t2f-s"
147				    "arm,arm1176jzf"
148				    "arm,arm1176jz-s"
149				    "arm,arm1176jzf-s"
150				    "arm,arm11mpcore"
151				    "arm,cortex-a5"
152				    "arm,cortex-a7"
153				    "arm,cortex-a8"
154				    "arm,cortex-a9"
155				    "arm,cortex-a12"
156				    "arm,cortex-a15"
157				    "arm,cortex-a17"
158				    "arm,cortex-a53"
159				    "arm,cortex-a57"
160				    "arm,cortex-m0"
161				    "arm,cortex-m0+"
162				    "arm,cortex-m1"
163				    "arm,cortex-m3"
164				    "arm,cortex-m4"
165				    "arm,cortex-r4"
166				    "arm,cortex-r5"
167				    "arm,cortex-r7"
168				    "brcm,brahma-b15"
169				    "cavium,thunder"
170				    "faraday,fa526"
171				    "intel,sa110"
172				    "intel,sa1100"
173				    "marvell,feroceon"
174				    "marvell,mohawk"
175				    "marvell,pj4a"
176				    "marvell,pj4b"
177				    "marvell,sheeva-v5"
178				    "nvidia,tegra132-denver"
179				    "qcom,krait"
180				    "qcom,scorpion"
181		- enable-method
182			Value type: <stringlist>
183			Usage and definition depend on ARM architecture version.
184				# On ARM v8 64-bit this property is required and must
185				  be one of:
186				     "psci"
187				     "spin-table"
188				# On ARM 32-bit systems this property is optional and
189				  can be one of:
190				    "allwinner,sun6i-a31"
191				    "allwinner,sun8i-a23"
192				    "arm,psci"
193				    "brcm,brahma-b15"
194				    "marvell,armada-375-smp"
195				    "marvell,armada-380-smp"
196				    "marvell,armada-390-smp"
197				    "marvell,armada-xp-smp"
198				    "qcom,gcc-msm8660"
199				    "qcom,kpss-acc-v1"
200				    "qcom,kpss-acc-v2"
201				    "rockchip,rk3066-smp"
202				    "ste,dbx500-smp"
203	
204		- cpu-release-addr
205			Usage: required for systems that have an "enable-method"
206			       property value of "spin-table".
207			Value type: <prop-encoded-array>
208			Definition:
209				# On ARM v8 64-bit systems must be a two cell
210				  property identifying a 64-bit zero-initialised
211				  memory location.
212	
213		- qcom,saw
214			Usage: required for systems that have an "enable-method"
215			       property value of "qcom,kpss-acc-v1" or
216			       "qcom,kpss-acc-v2"
217			Value type: <phandle>
218			Definition: Specifies the SAW[1] node associated with this CPU.
219	
220		- qcom,acc
221			Usage: required for systems that have an "enable-method"
222			       property value of "qcom,kpss-acc-v1" or
223			       "qcom,kpss-acc-v2"
224			Value type: <phandle>
225			Definition: Specifies the ACC[2] node associated with this CPU.
226	
227		- cpu-idle-states
228			Usage: Optional
229			Value type: <prop-encoded-array>
230			Definition:
231				# List of phandles to idle state nodes supported
232				  by this cpu [3].
233	
234		- rockchip,pmu
235			Usage: optional for systems that have an "enable-method"
236			       property value of "rockchip,rk3066-smp"
237			       While optional, it is the preferred way to get access to
238			       the cpu-core power-domains.
239			Value type: <phandle>
240			Definition: Specifies the syscon node controlling the cpu core
241				    power domains.
242	
243	Example 1 (dual-cluster big.LITTLE system 32-bit):
244	
245		cpus {
246			#size-cells = <0>;
247			#address-cells = <1>;
248	
249			cpu@0 {
250				device_type = "cpu";
251				compatible = "arm,cortex-a15";
252				reg = <0x0>;
253			};
254	
255			cpu@1 {
256				device_type = "cpu";
257				compatible = "arm,cortex-a15";
258				reg = <0x1>;
259			};
260	
261			cpu@100 {
262				device_type = "cpu";
263				compatible = "arm,cortex-a7";
264				reg = <0x100>;
265			};
266	
267			cpu@101 {
268				device_type = "cpu";
269				compatible = "arm,cortex-a7";
270				reg = <0x101>;
271			};
272		};
273	
274	Example 2 (Cortex-A8 uniprocessor 32-bit system):
275	
276		cpus {
277			#size-cells = <0>;
278			#address-cells = <1>;
279	
280			cpu@0 {
281				device_type = "cpu";
282				compatible = "arm,cortex-a8";
283				reg = <0x0>;
284			};
285		};
286	
287	Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
288	
289		cpus {
290			#size-cells = <0>;
291			#address-cells = <1>;
292	
293			cpu@0 {
294				device_type = "cpu";
295				compatible = "arm,arm926ej-s";
296				reg = <0x0>;
297			};
298		};
299	
300	Example 4 (ARM Cortex-A57 64-bit system):
301	
302	cpus {
303		#size-cells = <0>;
304		#address-cells = <2>;
305	
306		cpu@0 {
307			device_type = "cpu";
308			compatible = "arm,cortex-a57";
309			reg = <0x0 0x0>;
310			enable-method = "spin-table";
311			cpu-release-addr = <0 0x20000000>;
312		};
313	
314		cpu@1 {
315			device_type = "cpu";
316			compatible = "arm,cortex-a57";
317			reg = <0x0 0x1>;
318			enable-method = "spin-table";
319			cpu-release-addr = <0 0x20000000>;
320		};
321	
322		cpu@100 {
323			device_type = "cpu";
324			compatible = "arm,cortex-a57";
325			reg = <0x0 0x100>;
326			enable-method = "spin-table";
327			cpu-release-addr = <0 0x20000000>;
328		};
329	
330		cpu@101 {
331			device_type = "cpu";
332			compatible = "arm,cortex-a57";
333			reg = <0x0 0x101>;
334			enable-method = "spin-table";
335			cpu-release-addr = <0 0x20000000>;
336		};
337	
338		cpu@10000 {
339			device_type = "cpu";
340			compatible = "arm,cortex-a57";
341			reg = <0x0 0x10000>;
342			enable-method = "spin-table";
343			cpu-release-addr = <0 0x20000000>;
344		};
345	
346		cpu@10001 {
347			device_type = "cpu";
348			compatible = "arm,cortex-a57";
349			reg = <0x0 0x10001>;
350			enable-method = "spin-table";
351			cpu-release-addr = <0 0x20000000>;
352		};
353	
354		cpu@10100 {
355			device_type = "cpu";
356			compatible = "arm,cortex-a57";
357			reg = <0x0 0x10100>;
358			enable-method = "spin-table";
359			cpu-release-addr = <0 0x20000000>;
360		};
361	
362		cpu@10101 {
363			device_type = "cpu";
364			compatible = "arm,cortex-a57";
365			reg = <0x0 0x10101>;
366			enable-method = "spin-table";
367			cpu-release-addr = <0 0x20000000>;
368		};
369	
370		cpu@100000000 {
371			device_type = "cpu";
372			compatible = "arm,cortex-a57";
373			reg = <0x1 0x0>;
374			enable-method = "spin-table";
375			cpu-release-addr = <0 0x20000000>;
376		};
377	
378		cpu@100000001 {
379			device_type = "cpu";
380			compatible = "arm,cortex-a57";
381			reg = <0x1 0x1>;
382			enable-method = "spin-table";
383			cpu-release-addr = <0 0x20000000>;
384		};
385	
386		cpu@100000100 {
387			device_type = "cpu";
388			compatible = "arm,cortex-a57";
389			reg = <0x1 0x100>;
390			enable-method = "spin-table";
391			cpu-release-addr = <0 0x20000000>;
392		};
393	
394		cpu@100000101 {
395			device_type = "cpu";
396			compatible = "arm,cortex-a57";
397			reg = <0x1 0x101>;
398			enable-method = "spin-table";
399			cpu-release-addr = <0 0x20000000>;
400		};
401	
402		cpu@100010000 {
403			device_type = "cpu";
404			compatible = "arm,cortex-a57";
405			reg = <0x1 0x10000>;
406			enable-method = "spin-table";
407			cpu-release-addr = <0 0x20000000>;
408		};
409	
410		cpu@100010001 {
411			device_type = "cpu";
412			compatible = "arm,cortex-a57";
413			reg = <0x1 0x10001>;
414			enable-method = "spin-table";
415			cpu-release-addr = <0 0x20000000>;
416		};
417	
418		cpu@100010100 {
419			device_type = "cpu";
420			compatible = "arm,cortex-a57";
421			reg = <0x1 0x10100>;
422			enable-method = "spin-table";
423			cpu-release-addr = <0 0x20000000>;
424		};
425	
426		cpu@100010101 {
427			device_type = "cpu";
428			compatible = "arm,cortex-a57";
429			reg = <0x1 0x10101>;
430			enable-method = "spin-table";
431			cpu-release-addr = <0 0x20000000>;
432		};
433	};
434	
435	--
436	[1] arm/msm/qcom,saw2.txt
437	[2] arm/msm/qcom,kpss-acc.txt
438	[3] ARM Linux kernel documentation - idle states bindings
439	    Documentation/devicetree/bindings/arm/idle-states.txt
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