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Documentation / devicetree / bindings / arm / cpus.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	=================
2	ARM CPUs bindings
3	=================
4	
5	The device tree allows to describe the layout of CPUs in a system through
6	the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7	defining properties for every cpu.
8	
9	Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
10	
11	https://www.power.org/documentation/epapr-version-1-1/
12	
13	with updates for 32-bit and 64-bit ARM systems provided in this document.
14	
15	================================
16	Convention used in this document
17	================================
18	
19	This document follows the conventions described in the ePAPR v1.1, with
20	the addition:
21	
22	- square brackets define bitfields, eg reg[7:0] value of the bitfield in
23	  the reg property contained in bits 7 down to 0
24	
25	=====================================
26	cpus and cpu node bindings definition
27	=====================================
28	
29	The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30	nodes to be present and contain the properties described below.
31	
32	- cpus node
33	
34		Description: Container of cpu nodes
35	
36		The node name must be "cpus".
37	
38		A cpus node must define the following properties:
39	
40		- #address-cells
41			Usage: required
42			Value type: <u32>
43	
44			Definition depends on ARM architecture version and
45			configuration:
46	
47				# On uniprocessor ARM architectures previous to v7
48				  value must be 1, to enable a simple enumeration
49				  scheme for processors that do not have a HW CPU
50				  identification register.
51				# On 32-bit ARM 11 MPcore, ARM v7 or later systems
52				  value must be 1, that corresponds to CPUID/MPIDR
53				  registers sizes.
54				# On ARM v8 64-bit systems value should be set to 2,
55				  that corresponds to the MPIDR_EL1 register size.
56				  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57				  in the system, #address-cells can be set to 1, since
58				  MPIDR_EL1[63:32] bits are not used for CPUs
59				  identification.
60		- #size-cells
61			Usage: required
62			Value type: <u32>
63			Definition: must be set to 0
64	
65	- cpu node
66	
67		Description: Describes a CPU in an ARM based system
68	
69		PROPERTIES
70	
71		- device_type
72			Usage: required
73			Value type: <string>
74			Definition: must be "cpu"
75		- reg
76			Usage and definition depend on ARM architecture version and
77			configuration:
78	
79				# On uniprocessor ARM architectures previous to v7
80				  this property is required and must be set to 0.
81	
82				# On ARM 11 MPcore based systems this property is
83				  required and matches the CPUID[11:0] register bits.
84	
85				  Bits [11:0] in the reg cell must be set to
86				  bits [11:0] in CPU ID register.
87	
88				  All other bits in the reg cell must be set to 0.
89	
90				# On 32-bit ARM v7 or later systems this property is
91				  required and matches the CPU MPIDR[23:0] register
92				  bits.
93	
94				  Bits [23:0] in the reg cell must be set to
95				  bits [23:0] in MPIDR.
96	
97				  All other bits in the reg cell must be set to 0.
98	
99				# On ARM v8 64-bit systems this property is required
100				  and matches the MPIDR_EL1 register affinity bits.
101	
102				  * If cpus node's #address-cells property is set to 2
103	
104				    The first reg cell bits [7:0] must be set to
105				    bits [39:32] of MPIDR_EL1.
106	
107				    The second reg cell bits [23:0] must be set to
108				    bits [23:0] of MPIDR_EL1.
109	
110				  * If cpus node's #address-cells property is set to 1
111	
112				    The reg cell bits [23:0] must be set to bits [23:0]
113				    of MPIDR_EL1.
114	
115				  All other bits in the reg cells must be set to 0.
116	
117		- compatible:
118			Usage: required
119			Value type: <string>
120			Definition: should be one of:
121				    "arm,arm710t"
122				    "arm,arm720t"
123				    "arm,arm740t"
124				    "arm,arm7ej-s"
125				    "arm,arm7tdmi"
126				    "arm,arm7tdmi-s"
127				    "arm,arm9es"
128				    "arm,arm9ej-s"
129				    "arm,arm920t"
130				    "arm,arm922t"
131				    "arm,arm925"
132				    "arm,arm926e-s"
133				    "arm,arm926ej-s"
134				    "arm,arm940t"
135				    "arm,arm946e-s"
136				    "arm,arm966e-s"
137				    "arm,arm968e-s"
138				    "arm,arm9tdmi"
139				    "arm,arm1020e"
140				    "arm,arm1020t"
141				    "arm,arm1022e"
142				    "arm,arm1026ej-s"
143				    "arm,arm1136j-s"
144				    "arm,arm1136jf-s"
145				    "arm,arm1156t2-s"
146				    "arm,arm1156t2f-s"
147				    "arm,arm1176jzf"
148				    "arm,arm1176jz-s"
149				    "arm,arm1176jzf-s"
150				    "arm,arm11mpcore"
151				    "arm,cortex-a5"
152				    "arm,cortex-a7"
153				    "arm,cortex-a8"
154				    "arm,cortex-a9"
155				    "arm,cortex-a15"
156				    "arm,cortex-a53"
157				    "arm,cortex-a57"
158				    "arm,cortex-m0"
159				    "arm,cortex-m0+"
160				    "arm,cortex-m1"
161				    "arm,cortex-m3"
162				    "arm,cortex-m4"
163				    "arm,cortex-r4"
164				    "arm,cortex-r5"
165				    "arm,cortex-r7"
166				    "faraday,fa526"
167				    "intel,sa110"
168				    "intel,sa1100"
169				    "marvell,feroceon"
170				    "marvell,mohawk"
171				    "marvell,pj4a"
172				    "marvell,pj4b"
173				    "marvell,sheeva-v5"
174				    "qcom,krait"
175				    "qcom,scorpion"
176		- enable-method
177			Value type: <stringlist>
178			Usage and definition depend on ARM architecture version.
179				# On ARM v8 64-bit this property is required and must
180				  be one of:
181				     "psci"
182				     "spin-table"
183				# On ARM 32-bit systems this property is optional and
184				  can be one of:
185				    "allwinner,sun6i-a31"
186				    "arm,psci"
187				    "marvell,armada-375-smp"
188				    "marvell,armada-380-smp"
189				    "marvell,armada-xp-smp"
190				    "qcom,gcc-msm8660"
191				    "qcom,kpss-acc-v1"
192				    "qcom,kpss-acc-v2"
193				    "rockchip,rk3066-smp"
194	
195		- cpu-release-addr
196			Usage: required for systems that have an "enable-method"
197			       property value of "spin-table".
198			Value type: <prop-encoded-array>
199			Definition:
200				# On ARM v8 64-bit systems must be a two cell
201				  property identifying a 64-bit zero-initialised
202				  memory location.
203	
204		- qcom,saw
205			Usage: required for systems that have an "enable-method"
206			       property value of "qcom,kpss-acc-v1" or
207			       "qcom,kpss-acc-v2"
208			Value type: <phandle>
209			Definition: Specifies the SAW[1] node associated with this CPU.
210	
211		- qcom,acc
212			Usage: required for systems that have an "enable-method"
213			       property value of "qcom,kpss-acc-v1" or
214			       "qcom,kpss-acc-v2"
215			Value type: <phandle>
216			Definition: Specifies the ACC[2] node associated with this CPU.
217	
218	
219	Example 1 (dual-cluster big.LITTLE system 32-bit):
220	
221		cpus {
222			#size-cells = <0>;
223			#address-cells = <1>;
224	
225			cpu@0 {
226				device_type = "cpu";
227				compatible = "arm,cortex-a15";
228				reg = <0x0>;
229			};
230	
231			cpu@1 {
232				device_type = "cpu";
233				compatible = "arm,cortex-a15";
234				reg = <0x1>;
235			};
236	
237			cpu@100 {
238				device_type = "cpu";
239				compatible = "arm,cortex-a7";
240				reg = <0x100>;
241			};
242	
243			cpu@101 {
244				device_type = "cpu";
245				compatible = "arm,cortex-a7";
246				reg = <0x101>;
247			};
248		};
249	
250	Example 2 (Cortex-A8 uniprocessor 32-bit system):
251	
252		cpus {
253			#size-cells = <0>;
254			#address-cells = <1>;
255	
256			cpu@0 {
257				device_type = "cpu";
258				compatible = "arm,cortex-a8";
259				reg = <0x0>;
260			};
261		};
262	
263	Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
264	
265		cpus {
266			#size-cells = <0>;
267			#address-cells = <1>;
268	
269			cpu@0 {
270				device_type = "cpu";
271				compatible = "arm,arm926ej-s";
272				reg = <0x0>;
273			};
274		};
275	
276	Example 4 (ARM Cortex-A57 64-bit system):
277	
278	cpus {
279		#size-cells = <0>;
280		#address-cells = <2>;
281	
282		cpu@0 {
283			device_type = "cpu";
284			compatible = "arm,cortex-a57";
285			reg = <0x0 0x0>;
286			enable-method = "spin-table";
287			cpu-release-addr = <0 0x20000000>;
288		};
289	
290		cpu@1 {
291			device_type = "cpu";
292			compatible = "arm,cortex-a57";
293			reg = <0x0 0x1>;
294			enable-method = "spin-table";
295			cpu-release-addr = <0 0x20000000>;
296		};
297	
298		cpu@100 {
299			device_type = "cpu";
300			compatible = "arm,cortex-a57";
301			reg = <0x0 0x100>;
302			enable-method = "spin-table";
303			cpu-release-addr = <0 0x20000000>;
304		};
305	
306		cpu@101 {
307			device_type = "cpu";
308			compatible = "arm,cortex-a57";
309			reg = <0x0 0x101>;
310			enable-method = "spin-table";
311			cpu-release-addr = <0 0x20000000>;
312		};
313	
314		cpu@10000 {
315			device_type = "cpu";
316			compatible = "arm,cortex-a57";
317			reg = <0x0 0x10000>;
318			enable-method = "spin-table";
319			cpu-release-addr = <0 0x20000000>;
320		};
321	
322		cpu@10001 {
323			device_type = "cpu";
324			compatible = "arm,cortex-a57";
325			reg = <0x0 0x10001>;
326			enable-method = "spin-table";
327			cpu-release-addr = <0 0x20000000>;
328		};
329	
330		cpu@10100 {
331			device_type = "cpu";
332			compatible = "arm,cortex-a57";
333			reg = <0x0 0x10100>;
334			enable-method = "spin-table";
335			cpu-release-addr = <0 0x20000000>;
336		};
337	
338		cpu@10101 {
339			device_type = "cpu";
340			compatible = "arm,cortex-a57";
341			reg = <0x0 0x10101>;
342			enable-method = "spin-table";
343			cpu-release-addr = <0 0x20000000>;
344		};
345	
346		cpu@100000000 {
347			device_type = "cpu";
348			compatible = "arm,cortex-a57";
349			reg = <0x1 0x0>;
350			enable-method = "spin-table";
351			cpu-release-addr = <0 0x20000000>;
352		};
353	
354		cpu@100000001 {
355			device_type = "cpu";
356			compatible = "arm,cortex-a57";
357			reg = <0x1 0x1>;
358			enable-method = "spin-table";
359			cpu-release-addr = <0 0x20000000>;
360		};
361	
362		cpu@100000100 {
363			device_type = "cpu";
364			compatible = "arm,cortex-a57";
365			reg = <0x1 0x100>;
366			enable-method = "spin-table";
367			cpu-release-addr = <0 0x20000000>;
368		};
369	
370		cpu@100000101 {
371			device_type = "cpu";
372			compatible = "arm,cortex-a57";
373			reg = <0x1 0x101>;
374			enable-method = "spin-table";
375			cpu-release-addr = <0 0x20000000>;
376		};
377	
378		cpu@100010000 {
379			device_type = "cpu";
380			compatible = "arm,cortex-a57";
381			reg = <0x1 0x10000>;
382			enable-method = "spin-table";
383			cpu-release-addr = <0 0x20000000>;
384		};
385	
386		cpu@100010001 {
387			device_type = "cpu";
388			compatible = "arm,cortex-a57";
389			reg = <0x1 0x10001>;
390			enable-method = "spin-table";
391			cpu-release-addr = <0 0x20000000>;
392		};
393	
394		cpu@100010100 {
395			device_type = "cpu";
396			compatible = "arm,cortex-a57";
397			reg = <0x1 0x10100>;
398			enable-method = "spin-table";
399			cpu-release-addr = <0 0x20000000>;
400		};
401	
402		cpu@100010101 {
403			device_type = "cpu";
404			compatible = "arm,cortex-a57";
405			reg = <0x1 0x10101>;
406			enable-method = "spin-table";
407			cpu-release-addr = <0 0x20000000>;
408		};
409	};
410	
411	--
412	[1] arm/msm/qcom,saw2.txt
413	[2] arm/msm/qcom,kpss-acc.txt
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