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Documentation / devicetree / bindings / arm / pmu.txt


Based on kernel version 4.16.1. Page generated on 2018-04-09 11:52 EST.

1	* ARM Performance Monitor Units
2	
3	ARM cores often have a PMU for counting cpu and cache events like cache misses
4	and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
5	representation in the device tree should be done as under:-
6	
7	Required properties:
8	
9	- compatible : should be one of
10		"apm,potenza-pmu"
11		"arm,armv8-pmuv3"
12		"arm,cortex-a73-pmu"
13		"arm,cortex-a72-pmu"
14		"arm,cortex-a57-pmu"
15		"arm,cortex-a53-pmu"
16		"arm,cortex-a35-pmu"
17		"arm,cortex-a17-pmu"
18		"arm,cortex-a15-pmu"
19		"arm,cortex-a12-pmu"
20		"arm,cortex-a9-pmu"
21		"arm,cortex-a8-pmu"
22		"arm,cortex-a7-pmu"
23		"arm,cortex-a5-pmu"
24		"arm,arm11mpcore-pmu"
25		"arm,arm1176-pmu"
26		"arm,arm1136-pmu"
27		"brcm,vulcan-pmu"
28		"cavium,thunder-pmu"
29		"qcom,scorpion-pmu"
30		"qcom,scorpion-mp-pmu"
31		"qcom,krait-pmu"
32	- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
33	               interrupt (PPI) then 1 interrupt should be specified.
34	
35	Optional properties:
36	
37	- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
38	                       nodes corresponding directly to the affinity of
39			       the SPIs listed in the interrupts property.
40	
41	                       When using a PPI, specifies a list of phandles to CPU
42			       nodes corresponding to the set of CPUs which have
43			       a PMU of this type signalling the PPI listed in the
44			       interrupts property, unless this is already specified
45			       by the PPI interrupt specifier itself (in which case
46			       the interrupt-affinity property shouldn't be present).
47	
48	                       This property should be present when there is more than
49			       a single SPI.
50	
51	
52	- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
53	                     events.
54	
55	- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
56			      (SDER) is accessible. This will cause the driver to do
57			      any setup required that is only possible in ARMv7 secure
58			      state. If not present the ARMv7 SDER will not be touched,
59			      which means the PMU may fail to operate unless external
60			      code (bootloader or security monitor) has performed the
61			      appropriate initialisation. Note that this property is
62			      not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
63			      in Non-secure state.
64	
65	Example:
66	
67	pmu {
68	        compatible = "arm,cortex-a9-pmu";
69	        interrupts = <100 101>;
70	};
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