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Documentation / devicetree / bindings / arm / pmu.txt




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Based on kernel version 3.16. Page generated on 2014-08-06 21:36 EST.

1	* ARM Performance Monitor Units
2	
3	ARM cores often have a PMU for counting cpu and cache events like cache misses
4	and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
5	representation in the device tree should be done as under:-
6	
7	Required properties:
8	
9	- compatible : should be one of
10		"arm,armv8-pmuv3"
11		"arm,cortex-a17-pmu"
12		"arm,cortex-a15-pmu"
13		"arm,cortex-a12-pmu"
14		"arm,cortex-a9-pmu"
15		"arm,cortex-a8-pmu"
16		"arm,cortex-a7-pmu"
17		"arm,cortex-a5-pmu"
18		"arm,arm11mpcore-pmu"
19		"arm,arm1176-pmu"
20		"arm,arm1136-pmu"
21		"qcom,krait-pmu"
22	- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
23	               interrupt (PPI) then 1 interrupt should be specified.
24	
25	Optional properties:
26	
27	- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
28	                     events.
29	
30	Example:
31	
32	pmu {
33	        compatible = "arm,cortex-a9-pmu";
34	        interrupts = <100 101>;
35	};
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