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Documentation / devicetree / bindings / arm / pmu.txt




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Based on kernel version 4.3. Page generated on 2015-11-02 12:44 EST.

1	* ARM Performance Monitor Units
2	
3	ARM cores often have a PMU for counting cpu and cache events like cache misses
4	and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
5	representation in the device tree should be done as under:-
6	
7	Required properties:
8	
9	- compatible : should be one of
10		"arm,armv8-pmuv3"
11		"arm,cortex-a17-pmu"
12		"arm,cortex-a15-pmu"
13		"arm,cortex-a12-pmu"
14		"arm,cortex-a9-pmu"
15		"arm,cortex-a8-pmu"
16		"arm,cortex-a7-pmu"
17		"arm,cortex-a5-pmu"
18		"arm,arm11mpcore-pmu"
19		"arm,arm1176-pmu"
20		"arm,arm1136-pmu"
21		"qcom,scorpion-pmu"
22		"qcom,scorpion-mp-pmu"
23		"qcom,krait-pmu"
24	- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
25	               interrupt (PPI) then 1 interrupt should be specified.
26	
27	Optional properties:
28	
29	- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
30	                       nodes corresponding directly to the affinity of
31			       the SPIs listed in the interrupts property.
32	
33	                       When using a PPI, specifies a list of phandles to CPU
34			       nodes corresponding to the set of CPUs which have
35			       a PMU of this type signalling the PPI listed in the
36			       interrupts property.
37	
38	                       This property should be present when there is more than
39			       a single SPI.
40	
41	
42	- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
43	                     events.
44	
45	Example:
46	
47	pmu {
48	        compatible = "arm,cortex-a9-pmu";
49	        interrupts = <100 101>;
50	};
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