Based on kernel version 6.2.16
. Page generated on 2023-08-29 08:28 EST
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Graphics Clock & Reset Controller on SM8350 maintainers: - Robert Foss <robert.foss@linaro.org> description: | Qualcomm graphics clock control module provides the clocks, resets and power domains on Qualcomm SoCs. See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h properties: compatible: enum: - qcom,sm8350-gpucc clocks: items: - description: Board XO source - description: GPLL0 main branch source - description: GPLL0 div branch source '#clock-cells': const: 1 '#reset-cells': const: 1 '#power-domain-cells': const: 1 reg: maxItems: 1 required: - compatible - reg - clocks - '#clock-cells' - '#reset-cells' - '#power-domain-cells' additionalProperties: false examples: - | #include <dt-bindings/clock/qcom,gcc-sm8350.h> #include <dt-bindings/clock/qcom,rpmh.h> soc { #address-cells = <2>; #size-cells = <2>; clock-controller@3d90000 { compatible = "qcom,sm8350-gpucc"; reg = <0 0x03d90000 0 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; }; ... |