Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP i.MX8 Audio Clock Mux maintainers: - Shengjiu Wang <shengjiu.wang@nxp.com> description: | NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP used to control Audio related clock on the SoC. properties: compatible: enum: - fsl,imx8dxl-acm - fsl,imx8qm-acm - fsl,imx8qxp-acm reg: maxItems: 1 power-domains: minItems: 13 maxItems: 21 '#clock-cells': const: 1 description: The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h for the full list of i.MX8 ACM clock IDs. clocks: minItems: 13 maxItems: 27 clock-names: minItems: 13 maxItems: 27 required: - compatible - reg - power-domains - '#clock-cells' - clocks - clock-names allOf: - if: properties: compatible: contains: enum: - fsl,imx8qxp-acm then: properties: power-domains: items: - description: power domain of IMX_SC_R_AUDIO_CLK_0 - description: power domain of IMX_SC_R_AUDIO_CLK_1 - description: power domain of IMX_SC_R_MCLK_OUT_0 - description: power domain of IMX_SC_R_MCLK_OUT_1 - description: power domain of IMX_SC_R_AUDIO_PLL_0 - description: power domain of IMX_SC_R_AUDIO_PLL_1 - description: power domain of IMX_SC_R_ASRC_0 - description: power domain of IMX_SC_R_ASRC_1 - description: power domain of IMX_SC_R_ESAI_0 - description: power domain of IMX_SC_R_SAI_0 - description: power domain of IMX_SC_R_SAI_1 - description: power domain of IMX_SC_R_SAI_2 - description: power domain of IMX_SC_R_SAI_3 - description: power domain of IMX_SC_R_SAI_4 - description: power domain of IMX_SC_R_SAI_5 - description: power domain of IMX_SC_R_SPDIF_0 - description: power domain of IMX_SC_R_MQS_0 clocks: minItems: 18 maxItems: 18 clock-names: items: - const: aud_rec_clk0_lpcg_clk - const: aud_rec_clk1_lpcg_clk - const: aud_pll_div_clk0_lpcg_clk - const: aud_pll_div_clk1_lpcg_clk - const: ext_aud_mclk0 - const: ext_aud_mclk1 - const: esai0_rx_clk - const: esai0_rx_hf_clk - const: esai0_tx_clk - const: esai0_tx_hf_clk - const: spdif0_rx - const: sai0_rx_bclk - const: sai0_tx_bclk - const: sai1_rx_bclk - const: sai1_tx_bclk - const: sai2_rx_bclk - const: sai3_rx_bclk - const: sai4_rx_bclk - if: properties: compatible: contains: enum: - fsl,imx8qm-acm then: properties: power-domains: items: - description: power domain of IMX_SC_R_AUDIO_CLK_0 - description: power domain of IMX_SC_R_AUDIO_CLK_1 - description: power domain of IMX_SC_R_MCLK_OUT_0 - description: power domain of IMX_SC_R_MCLK_OUT_1 - description: power domain of IMX_SC_R_AUDIO_PLL_0 - description: power domain of IMX_SC_R_AUDIO_PLL_1 - description: power domain of IMX_SC_R_ASRC_0 - description: power domain of IMX_SC_R_ASRC_1 - description: power domain of IMX_SC_R_ESAI_0 - description: power domain of IMX_SC_R_ESAI_1 - description: power domain of IMX_SC_R_SAI_0 - description: power domain of IMX_SC_R_SAI_1 - description: power domain of IMX_SC_R_SAI_2 - description: power domain of IMX_SC_R_SAI_3 - description: power domain of IMX_SC_R_SAI_4 - description: power domain of IMX_SC_R_SAI_5 - description: power domain of IMX_SC_R_SAI_6 - description: power domain of IMX_SC_R_SAI_7 - description: power domain of IMX_SC_R_SPDIF_0 - description: power domain of IMX_SC_R_SPDIF_1 - description: power domain of IMX_SC_R_MQS_0 clocks: minItems: 27 maxItems: 27 clock-names: items: - const: aud_rec_clk0_lpcg_clk - const: aud_rec_clk1_lpcg_clk - const: aud_pll_div_clk0_lpcg_clk - const: aud_pll_div_clk1_lpcg_clk - const: mlb_clk - const: hdmi_rx_mclk - const: ext_aud_mclk0 - const: ext_aud_mclk1 - const: esai0_rx_clk - const: esai0_rx_hf_clk - const: esai0_tx_clk - const: esai0_tx_hf_clk - const: esai1_rx_clk - const: esai1_rx_hf_clk - const: esai1_tx_clk - const: esai1_tx_hf_clk - const: spdif0_rx - const: spdif1_rx - const: sai0_rx_bclk - const: sai0_tx_bclk - const: sai1_rx_bclk - const: sai1_tx_bclk - const: sai2_rx_bclk - const: sai3_rx_bclk - const: sai4_rx_bclk - const: sai5_tx_bclk - const: sai6_rx_bclk - if: properties: compatible: contains: enum: - fsl,imx8dxl-acm then: properties: power-domains: items: - description: power domain of IMX_SC_R_AUDIO_CLK_0 - description: power domain of IMX_SC_R_AUDIO_CLK_1 - description: power domain of IMX_SC_R_MCLK_OUT_0 - description: power domain of IMX_SC_R_MCLK_OUT_1 - description: power domain of IMX_SC_R_AUDIO_PLL_0 - description: power domain of IMX_SC_R_AUDIO_PLL_1 - description: power domain of IMX_SC_R_ASRC_0 - description: power domain of IMX_SC_R_SAI_0 - description: power domain of IMX_SC_R_SAI_1 - description: power domain of IMX_SC_R_SAI_2 - description: power domain of IMX_SC_R_SAI_3 - description: power domain of IMX_SC_R_SPDIF_0 - description: power domain of IMX_SC_R_MQS_0 clocks: minItems: 13 maxItems: 13 clock-names: items: - const: aud_rec_clk0_lpcg_clk - const: aud_rec_clk1_lpcg_clk - const: aud_pll_div_clk0_lpcg_clk - const: aud_pll_div_clk1_lpcg_clk - const: ext_aud_mclk0 - const: ext_aud_mclk1 - const: spdif0_rx - const: sai0_rx_bclk - const: sai0_tx_bclk - const: sai1_rx_bclk - const: sai1_tx_bclk - const: sai2_rx_bclk - const: sai3_rx_bclk additionalProperties: false examples: # Clock Control Module node: - | #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> clock-controller@59e00000 { compatible = "fsl,imx8qxp-acm"; reg = <0x59e00000 0x1d0000>; #clock-cells = <1>; power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, <&pd IMX_SC_R_AUDIO_CLK_1>, <&pd IMX_SC_R_MCLK_OUT_0>, <&pd IMX_SC_R_MCLK_OUT_1>, <&pd IMX_SC_R_AUDIO_PLL_0>, <&pd IMX_SC_R_AUDIO_PLL_1>, <&pd IMX_SC_R_ASRC_0>, <&pd IMX_SC_R_ASRC_1>, <&pd IMX_SC_R_ESAI_0>, <&pd IMX_SC_R_SAI_0>, <&pd IMX_SC_R_SAI_1>, <&pd IMX_SC_R_SAI_2>, <&pd IMX_SC_R_SAI_3>, <&pd IMX_SC_R_SAI_4>, <&pd IMX_SC_R_SAI_5>, <&pd IMX_SC_R_SPDIF_0>, <&pd IMX_SC_R_MQS_0>; clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, <&aud_rec1_lpcg IMX_LPCG_CLK_0>, <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, <&clk_ext_aud_mclk0>, <&clk_ext_aud_mclk1>, <&clk_esai0_rx_clk>, <&clk_esai0_rx_hf_clk>, <&clk_esai0_tx_clk>, <&clk_esai0_tx_hf_clk>, <&clk_spdif0_rx>, <&clk_sai0_rx_bclk>, <&clk_sai0_tx_bclk>, <&clk_sai1_rx_bclk>, <&clk_sai1_tx_bclk>, <&clk_sai2_rx_bclk>, <&clk_sai3_rx_bclk>, <&clk_sai4_rx_bclk>; clock-names = "aud_rec_clk0_lpcg_clk", "aud_rec_clk1_lpcg_clk", "aud_pll_div_clk0_lpcg_clk", "aud_pll_div_clk1_lpcg_clk", "ext_aud_mclk0", "ext_aud_mclk1", "esai0_rx_clk", "esai0_rx_hf_clk", "esai0_tx_clk", "esai0_tx_hf_clk", "spdif0_rx", "sai0_rx_bclk", "sai0_tx_bclk", "sai1_rx_bclk", "sai1_tx_bclk", "sai2_rx_bclk", "sai3_rx_bclk", "sai4_rx_bclk"; }; |