Based on kernel version 6.8. Page generated on 2024-03-11 21:26 EST.
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung Exynos7 SoC clock controller maintainers: - Chanwoo Choi <cw00.choi@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> - Sylwester Nawrocki <s.nawrocki@samsung.com> - Tomasz Figa <tomasz.figa@gmail.com> description: | Expected external clocks, defined in DTS as fixed-rate clocks with a matching name:: - "fin_pll" - PLL input clock from XXTI All available clocks are defined as preprocessor macros in include/dt-bindings/clock/exynos7-clk.h header. properties: compatible: enum: - samsung,exynos7-clock-topc - samsung,exynos7-clock-top0 - samsung,exynos7-clock-top1 - samsung,exynos7-clock-ccore - samsung,exynos7-clock-peric0 - samsung,exynos7-clock-peric1 - samsung,exynos7-clock-peris - samsung,exynos7-clock-fsys0 - samsung,exynos7-clock-fsys1 - samsung,exynos7-clock-mscl - samsung,exynos7-clock-aud clocks: minItems: 1 maxItems: 13 clock-names: minItems: 1 maxItems: 13 "#clock-cells": const: 1 reg: maxItems: 1 required: - compatible - "#clock-cells" - reg allOf: - if: properties: compatible: contains: const: samsung,exynos7-clock-top0 then: properties: clocks: minItems: 6 maxItems: 6 clock-names: items: - const: fin_pll - const: dout_sclk_bus0_pll - const: dout_sclk_bus1_pll - const: dout_sclk_cc_pll - const: dout_sclk_mfc_pll - const: dout_sclk_aud_pll required: - clock-names - clocks - if: properties: compatible: contains: const: samsung,exynos7-clock-top1 then: properties: clocks: minItems: 5 maxItems: 5 clock-names: items: - const: fin_pll - const: dout_sclk_bus0_pll - const: dout_sclk_bus1_pll - const: dout_sclk_cc_pll - const: dout_sclk_mfc_pll required: - clock-names - clocks - if: properties: compatible: contains: const: samsung,exynos7-clock-ccore then: properties: clocks: minItems: 2 maxItems: 2 clock-names: items: - const: fin_pll - const: dout_aclk_ccore_133 required: - clock-names - clocks - if: properties: compatible: contains: const: samsung,exynos7-clock-peric0 then: properties: clocks: minItems: 3 maxItems: 3 clock-names: items: - const: fin_pll - const: dout_aclk_peric0_66 - const: sclk_uart0 required: - clock-names - clocks - if: properties: compatible: contains: const: samsung,exynos7-clock-peric1 then: properties: clocks: minItems: 13 maxItems: 13 clock-names: items: - const: fin_pll - const: dout_aclk_peric1_66 - const: sclk_uart1 - const: sclk_uart2 - const: sclk_uart3 - const: sclk_spi0 - const: sclk_spi1 - const: sclk_spi2 - const: sclk_spi3 - const: sclk_spi4 - const: sclk_i2s1 - const: sclk_pcm1 - const: sclk_spdif required: - clock-names - clocks - if: properties: compatible: contains: const: samsung,exynos7-clock-peris then: properties: clocks: minItems: 2 maxItems: 2 clock-names: items: - const: fin_pll - const: dout_aclk_peris_66 required: - clock-names - clocks - if: properties: compatible: contains: const: samsung,exynos7-clock-fsys0 then: properties: clocks: minItems: 3 maxItems: 3 clock-names: items: - const: fin_pll - const: dout_aclk_fsys0_200 - const: dout_sclk_mmc2 required: - clock-names - clocks - if: properties: compatible: contains: const: samsung,exynos7-clock-fsys1 then: properties: clocks: minItems: 7 maxItems: 7 clock-names: items: - const: fin_pll - const: dout_aclk_fsys1_200 - const: dout_sclk_mmc0 - const: dout_sclk_mmc1 - const: dout_sclk_ufsunipro20 - const: dout_sclk_phy_fsys1 - const: dout_sclk_phy_fsys1_26m required: - clock-names - clocks - if: properties: compatible: contains: const: samsung,exynos7-clock-aud then: properties: clocks: minItems: 2 maxItems: 2 clock-names: items: - const: fin_pll - const: fout_aud_pll required: - clock-names - clocks additionalProperties: false examples: - | #include <dt-bindings/clock/exynos7-clk.h> fin_pll: clock { compatible = "fixed-clock"; clock-output-names = "fin_pll"; #clock-cells = <0>; clock-frequency = <24000000>; }; clock-controller@105e0000 { compatible = "samsung,exynos7-clock-top1"; reg = <0x105e0000 0xb000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, <&clock_topc DOUT_SCLK_BUS1_PLL>, <&clock_topc DOUT_SCLK_CC_PLL>, <&clock_topc DOUT_SCLK_MFC_PLL>; clock-names = "fin_pll", "dout_sclk_bus0_pll", "dout_sclk_bus1_pll", "dout_sclk_cc_pll", "dout_sclk_mfc_pll"; }; |