# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7110 System-Top-Group Clock and Reset Generator

maintainers:
  - Xingyu Wu <xingyu.wu@starfivetech.com>

properties:
  compatible:
    const: starfive,jh7110-stgcrg

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Main Oscillator (24 MHz)
      - description: HIFI4 core
      - description: STG AXI/AHB
      - description: USB (125 MHz)
      - description: CPU Bus
      - description: HIFI4 Axi
      - description: NOC STG Bus
      - description: APB Bus

  clock-names:
    items:
      - const: osc
      - const: hifi4_core
      - const: stg_axiahb
      - const: usb_125m
      - const: cpu_bus
      - const: hifi4_axi
      - const: nocstg_bus
      - const: apb_bus
 
  '#clock-cells':
    const: 1
    description:
      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
 
  '#reset-cells':
    const: 1
    description:
      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/starfive,jh7110-crg.h>
 
    stgcrg: clock-controller@10230000 {
        compatible = "starfive,jh7110-stgcrg";
        reg = <0x10230000 0x10000>;
        clocks = <&osc>,
                 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
                 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
                 <&syscrg JH7110_SYSCLK_USB_125M>,
                 <&syscrg JH7110_SYSCLK_CPU_BUS>,
                 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
                 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
                 <&syscrg JH7110_SYSCLK_APB_BUS>;
        clock-names = "osc", "hifi4_core",
                      "stg_axiahb", "usb_125m",
                      "cpu_bus", "hifi4_axi",
                      "nocstg_bus", "apb_bus";
        #clock-cells = <1>;
        #reset-cells = <1>;
    };