# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator

maintainers:
  - Xingyu Wu <xingyu.wu@starfivetech.com>

properties:
  compatible:
    const: starfive,jh7110-ispcrg

  reg:
    maxItems: 1

  clocks:
    items:
      - description: ISP Top core
      - description: ISP Top Axi
      - description: NOC ISP Bus
      - description: external DVP

  clock-names:
    items:
      - const: isp_top_core
      - const: isp_top_axi
      - const: noc_bus_isp_axi
      - const: dvp_clk

  resets:
    items:
      - description: ISP Top core
      - description: ISP Top Axi
      - description: NOC ISP Bus
 
  '#clock-cells':
    const: 1
    description:
      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
 
  '#reset-cells':
    const: 1
    description:
      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.

  power-domains:
    maxItems: 1
    description:
      ISP domain power

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - '#clock-cells'
  - '#reset-cells'
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/starfive,jh7110-crg.h>
    #include <dt-bindings/power/starfive,jh7110-pmu.h>
    #include <dt-bindings/reset/starfive,jh7110-crg.h>
 
    ispcrg: clock-controller@19810000 {
        compatible = "starfive,jh7110-ispcrg";
        reg = <0x19810000 0x10000>;
        clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
                 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
                 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
                 <&dvp_clk>;
        clock-names = "isp_top_core", "isp_top_axi",
                      "noc_bus_isp_axi", "dvp_clk";
        resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
                 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
                 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        power-domains = <&pwrc JH7110_PD_ISP>;
    };