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Based on kernel version 4.1. Page generated on 2015-06-28 12:13 EST.

1	PINCTRL (PIN CONTROL) subsystem
2	This document outlines the pin control subsystem in Linux
3	
4	This subsystem deals with:
5	
6	- Enumerating and naming controllable pins
7	
8	- Multiplexing of pins, pads, fingers (etc) see below for details
9	
10	- Configuration of pins, pads, fingers (etc), such as software-controlled
11	  biasing and driving mode specific pins, such as pull-up/down, open drain,
12	  load capacitance etc.
13	
14	Top-level interface
15	===================
16	
17	Definition of PIN CONTROLLER:
18	
19	- A pin controller is a piece of hardware, usually a set of registers, that
20	  can control PINs. It may be able to multiplex, bias, set load capacitance,
21	  set drive strength, etc. for individual pins or groups of pins.
22	
23	Definition of PIN:
24	
25	- PINS are equal to pads, fingers, balls or whatever packaging input or
26	  output line you want to control and these are denoted by unsigned integers
27	  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28	  there may be several such number spaces in a system. This pin space may
29	  be sparse - i.e. there may be gaps in the space with numbers where no
30	  pin exists.
31	
32	When a PIN CONTROLLER is instantiated, it will register a descriptor to the
33	pin control framework, and this descriptor contains an array of pin descriptors
34	describing the pins handled by this specific pin controller.
35	
36	Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
37	
38	        A   B   C   D   E   F   G   H
39	
40	   8    o   o   o   o   o   o   o   o
41	
42	   7    o   o   o   o   o   o   o   o
43	
44	   6    o   o   o   o   o   o   o   o
45	
46	   5    o   o   o   o   o   o   o   o
47	
48	   4    o   o   o   o   o   o   o   o
49	
50	   3    o   o   o   o   o   o   o   o
51	
52	   2    o   o   o   o   o   o   o   o
53	
54	   1    o   o   o   o   o   o   o   o
55	
56	To register a pin controller and name all the pins on this package we can do
57	this in our driver:
58	
59	#include <linux/pinctrl/pinctrl.h>
60	
61	const struct pinctrl_pin_desc foo_pins[] = {
62	      PINCTRL_PIN(0, "A8"),
63	      PINCTRL_PIN(1, "B8"),
64	      PINCTRL_PIN(2, "C8"),
65	      ...
66	      PINCTRL_PIN(61, "F1"),
67	      PINCTRL_PIN(62, "G1"),
68	      PINCTRL_PIN(63, "H1"),
69	};
70	
71	static struct pinctrl_desc foo_desc = {
72		.name = "foo",
73		.pins = foo_pins,
74		.npins = ARRAY_SIZE(foo_pins),
75		.owner = THIS_MODULE,
76	};
77	
78	int __init foo_probe(void)
79	{
80		struct pinctrl_dev *pctl;
81	
82		pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
83		if (!pctl)
84			pr_err("could not register foo pin driver\n");
85	}
86	
87	To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
88	selected drivers, you need to select them from your machine's Kconfig entry,
89	since these are so tightly integrated with the machines they are used on.
90	See for example arch/arm/mach-u300/Kconfig for an example.
91	
92	Pins usually have fancier names than this. You can find these in the datasheet
93	for your chip. Notice that the core pinctrl.h file provides a fancy macro
94	called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
95	the pins from 0 in the upper left corner to 63 in the lower right corner.
96	This enumeration was arbitrarily chosen, in practice you need to think
97	through your numbering system so that it matches the layout of registers
98	and such things in your driver, or the code may become complicated. You must
99	also consider matching of offsets to the GPIO ranges that may be handled by
100	the pin controller.
101	
102	For a padring with 467 pads, as opposed to actual pins, I used an enumeration
103	like this, walking around the edge of the chip, which seems to be industry
104	standard too (all these pads had names, too):
105	
106	
107	     0 ..... 104
108	   466        105
109	     .        .
110	     .        .
111	   358        224
112	    357 .... 225
113	
114	
115	Pin groups
116	==========
117	
118	Many controllers need to deal with groups of pins, so the pin controller
119	subsystem has a mechanism for enumerating groups of pins and retrieving the
120	actual enumerated pins that are part of a certain group.
121	
122	For example, say that we have a group of pins dealing with an SPI interface
123	on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
124	on { 24, 25 }.
125	
126	These two groups are presented to the pin control subsystem by implementing
127	some generic pinctrl_ops like this:
128	
129	#include <linux/pinctrl/pinctrl.h>
130	
131	struct foo_group {
132		const char *name;
133		const unsigned int *pins;
134		const unsigned num_pins;
135	};
136	
137	static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
138	static const unsigned int i2c0_pins[] = { 24, 25 };
139	
140	static const struct foo_group foo_groups[] = {
141		{
142			.name = "spi0_grp",
143			.pins = spi0_pins,
144			.num_pins = ARRAY_SIZE(spi0_pins),
145		},
146		{
147			.name = "i2c0_grp",
148			.pins = i2c0_pins,
149			.num_pins = ARRAY_SIZE(i2c0_pins),
150		},
151	};
152	
153	
154	static int foo_get_groups_count(struct pinctrl_dev *pctldev)
155	{
156		return ARRAY_SIZE(foo_groups);
157	}
158	
159	static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
160					       unsigned selector)
161	{
162		return foo_groups[selector].name;
163	}
164	
165	static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
166				       const unsigned **pins,
167				       unsigned *num_pins)
168	{
169		*pins = (unsigned *) foo_groups[selector].pins;
170		*num_pins = foo_groups[selector].num_pins;
171		return 0;
172	}
173	
174	static struct pinctrl_ops foo_pctrl_ops = {
175		.get_groups_count = foo_get_groups_count,
176		.get_group_name = foo_get_group_name,
177		.get_group_pins = foo_get_group_pins,
178	};
179	
180	
181	static struct pinctrl_desc foo_desc = {
182	       ...
183	       .pctlops = &foo_pctrl_ops,
184	};
185	
186	The pin control subsystem will call the .get_groups_count() function to
187	determine the total number of legal selectors, then it will call the other functions
188	to retrieve the name and pins of the group. Maintaining the data structure of
189	the groups is up to the driver, this is just a simple example - in practice you
190	may need more entries in your group structure, for example specific register
191	ranges associated with each group and so on.
192	
193	
194	Pin configuration
195	=================
196	
197	Pins can sometimes be software-configured in various ways, mostly related
198	to their electronic properties when used as inputs or outputs. For example you
199	may be able to make an output pin high impedance, or "tristate" meaning it is
200	effectively disconnected. You may be able to connect an input pin to VDD or GND
201	using a certain resistor value - pull up and pull down - so that the pin has a
202	stable value when nothing is driving the rail it is connected to, or when it's
203	unconnected.
204	
205	Pin configuration can be programmed by adding configuration entries into the
206	mapping table; see section "Board/machine configuration" below.
207	
208	The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
209	above, is entirely defined by the pin controller driver.
210	
211	The pin configuration driver implements callbacks for changing pin
212	configuration in the pin controller ops like this:
213	
214	#include <linux/pinctrl/pinctrl.h>
215	#include <linux/pinctrl/pinconf.h>
216	#include "platform_x_pindefs.h"
217	
218	static int foo_pin_config_get(struct pinctrl_dev *pctldev,
219			    unsigned offset,
220			    unsigned long *config)
221	{
222		struct my_conftype conf;
223	
224		... Find setting for pin @ offset ...
225	
226		*config = (unsigned long) conf;
227	}
228	
229	static int foo_pin_config_set(struct pinctrl_dev *pctldev,
230			    unsigned offset,
231			    unsigned long config)
232	{
233		struct my_conftype *conf = (struct my_conftype *) config;
234	
235		switch (conf) {
236			case PLATFORM_X_PULL_UP:
237			...
238			}
239		}
240	}
241	
242	static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
243			    unsigned selector,
244			    unsigned long *config)
245	{
246		...
247	}
248	
249	static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
250			    unsigned selector,
251			    unsigned long config)
252	{
253		...
254	}
255	
256	static struct pinconf_ops foo_pconf_ops = {
257		.pin_config_get = foo_pin_config_get,
258		.pin_config_set = foo_pin_config_set,
259		.pin_config_group_get = foo_pin_config_group_get,
260		.pin_config_group_set = foo_pin_config_group_set,
261	};
262	
263	/* Pin config operations are handled by some pin controller */
264	static struct pinctrl_desc foo_desc = {
265		...
266		.confops = &foo_pconf_ops,
267	};
268	
269	Since some controllers have special logic for handling entire groups of pins
270	they can exploit the special whole-group pin control function. The
271	pin_config_group_set() callback is allowed to return the error code -EAGAIN,
272	for groups it does not want to handle, or if it just wants to do some
273	group-level handling and then fall through to iterate over all pins, in which
274	case each individual pin will be treated by separate pin_config_set() calls as
275	well.
276	
277	
278	Interaction with the GPIO subsystem
279	===================================
280	
281	The GPIO drivers may want to perform operations of various types on the same
282	physical pins that are also registered as pin controller pins.
283	
284	First and foremost, the two subsystems can be used as completely orthogonal,
285	see the section named "pin control requests from drivers" and
286	"drivers needing both pin control and GPIOs" below for details. But in some
287	situations a cross-subsystem mapping between pins and GPIOs is needed.
288	
289	Since the pin controller subsystem have its pinspace local to the pin
290	controller we need a mapping so that the pin control subsystem can figure out
291	which pin controller handles control of a certain GPIO pin. Since a single
292	pin controller may be muxing several GPIO ranges (typically SoCs that have
293	one set of pins, but internally several GPIO silicon blocks, each modelled as
294	a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
295	instance like this:
296	
297	struct gpio_chip chip_a;
298	struct gpio_chip chip_b;
299	
300	static struct pinctrl_gpio_range gpio_range_a = {
301		.name = "chip a",
302		.id = 0,
303		.base = 32,
304		.pin_base = 32,
305		.npins = 16,
306		.gc = &chip_a;
307	};
308	
309	static struct pinctrl_gpio_range gpio_range_b = {
310		.name = "chip b",
311		.id = 0,
312		.base = 48,
313		.pin_base = 64,
314		.npins = 8,
315		.gc = &chip_b;
316	};
317	
318	{
319		struct pinctrl_dev *pctl;
320		...
321		pinctrl_add_gpio_range(pctl, &gpio_range_a);
322		pinctrl_add_gpio_range(pctl, &gpio_range_b);
323	}
324	
325	So this complex system has one pin controller handling two different
326	GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
327	"chip b" have different .pin_base, which means a start pin number of the
328	GPIO range.
329	
330	The GPIO range of "chip a" starts from the GPIO base of 32 and actual
331	pin range also starts from 32. However "chip b" has different starting
332	offset for the GPIO range and pin range. The GPIO range of "chip b" starts
333	from GPIO number 48, while the pin range of "chip b" starts from 64.
334	
335	We can convert a gpio number to actual pin number using this "pin_base".
336	They are mapped in the global GPIO pin space at:
337	
338	chip a:
339	 - GPIO range : [32 .. 47]
340	 - pin range  : [32 .. 47]
341	chip b:
342	 - GPIO range : [48 .. 55]
343	 - pin range  : [64 .. 71]
344	
345	The above examples assume the mapping between the GPIOs and pins is
346	linear. If the mapping is sparse or haphazard, an array of arbitrary pin
347	numbers can be encoded in the range like this:
348	
349	static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
350	
351	static struct pinctrl_gpio_range gpio_range = {
352		.name = "chip",
353		.id = 0,
354		.base = 32,
355		.pins = &range_pins,
356		.npins = ARRAY_SIZE(range_pins),
357		.gc = &chip;
358	};
359	
360	In this case the pin_base property will be ignored. If the name of a pin
361	group is known, the pins and npins elements of the above structure can be
362	initialised using the function pinctrl_get_group_pins(), e.g. for pin
363	group "foo":
364	
365	pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
366	
367	When GPIO-specific functions in the pin control subsystem are called, these
368	ranges will be used to look up the appropriate pin controller by inspecting
369	and matching the pin to the pin ranges across all controllers. When a
370	pin controller handling the matching range is found, GPIO-specific functions
371	will be called on that specific pin controller.
372	
373	For all functionalities dealing with pin biasing, pin muxing etc, the pin
374	controller subsystem will look up the corresponding pin number from the passed
375	in gpio number, and use the range's internals to retrieve a pin number. After
376	that, the subsystem passes it on to the pin control driver, so the driver
377	will get a pin number into its handled number range. Further it is also passed
378	the range ID value, so that the pin controller knows which range it should
379	deal with.
380	
381	Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
382	section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
383	pinctrl and gpio drivers.
384	
385	
386	PINMUX interfaces
387	=================
388	
389	These calls use the pinmux_* naming prefix.  No other calls should use that
390	prefix.
391	
392	
393	What is pinmuxing?
394	==================
395	
396	PINMUX, also known as padmux, ballmux, alternate functions or mission modes
397	is a way for chip vendors producing some kind of electrical packages to use
398	a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
399	functions, depending on the application. By "application" in this context
400	we usually mean a way of soldering or wiring the package into an electronic
401	system, even though the framework makes it possible to also change the function
402	at runtime.
403	
404	Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
405	
406	        A   B   C   D   E   F   G   H
407	      +---+
408	   8  | o | o   o   o   o   o   o   o
409	      |   |
410	   7  | o | o   o   o   o   o   o   o
411	      |   |
412	   6  | o | o   o   o   o   o   o   o
413	      +---+---+
414	   5  | o | o | o   o   o   o   o   o
415	      +---+---+               +---+
416	   4    o   o   o   o   o   o | o | o
417	                              |   |
418	   3    o   o   o   o   o   o | o | o
419	                              |   |
420	   2    o   o   o   o   o   o | o | o
421	      +-------+-------+-------+---+---+
422	   1  | o   o | o   o | o   o | o | o |
423	      +-------+-------+-------+---+---+
424	
425	This is not tetris. The game to think of is chess. Not all PGA/BGA packages
426	are chessboard-like, big ones have "holes" in some arrangement according to
427	different design patterns, but we're using this as a simple example. Of the
428	pins you see some will be taken by things like a few VCC and GND to feed power
429	to the chip, and quite a few will be taken by large ports like an external
430	memory interface. The remaining pins will often be subject to pin multiplexing.
431	
432	The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
433	to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
434	pinctrl_register_pins() and a suitable data set as shown earlier.
435	
436	In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
437	(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
438	some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
439	be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
440	we cannot use the SPI port and I2C port at the same time. However in the inside
441	of the package the silicon performing the SPI logic can alternatively be routed
442	out on pins { G4, G3, G2, G1 }.
443	
444	On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
445	special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
446	consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
447	{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
448	port on pins { G4, G3, G2, G1 } of course.
449	
450	This way the silicon blocks present inside the chip can be multiplexed "muxed"
451	out on different pin ranges. Often contemporary SoC (systems on chip) will
452	contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
453	different pins by pinmux settings.
454	
455	Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
456	common to be able to use almost any pin as a GPIO pin if it is not currently
457	in use by some other I/O port.
458	
459	
460	Pinmux conventions
461	==================
462	
463	The purpose of the pinmux functionality in the pin controller subsystem is to
464	abstract and provide pinmux settings to the devices you choose to instantiate
465	in your machine configuration. It is inspired by the clk, GPIO and regulator
466	subsystems, so devices will request their mux setting, but it's also possible
467	to request a single pin for e.g. GPIO.
468	
469	Definitions:
470	
471	- FUNCTIONS can be switched in and out by a driver residing with the pin
472	  control subsystem in the drivers/pinctrl/* directory of the kernel. The
473	  pin control driver knows the possible functions. In the example above you can
474	  identify three pinmux functions, one for spi, one for i2c and one for mmc.
475	
476	- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
477	  In this case the array could be something like: { spi0, i2c0, mmc0 }
478	  for the three available functions.
479	
480	- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
481	  function is *always* associated with a certain set of pin groups, could
482	  be just a single one, but could also be many. In the example above the
483	  function i2c is associated with the pins { A5, B5 }, enumerated as
484	  { 24, 25 } in the controller pin space.
485	
486	  The Function spi is associated with pin groups { A8, A7, A6, A5 }
487	  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
488	  { 38, 46, 54, 62 } respectively.
489	
490	  Group names must be unique per pin controller, no two groups on the same
491	  controller may have the same name.
492	
493	- The combination of a FUNCTION and a PIN GROUP determine a certain function
494	  for a certain set of pins. The knowledge of the functions and pin groups
495	  and their machine-specific particulars are kept inside the pinmux driver,
496	  from the outside only the enumerators are known, and the driver core can:
497	
498	  - Request the name of a function with a certain selector (>= 0)
499	  - A list of groups associated with a certain function
500	  - Request that a certain group in that list to be activated for a certain
501	    function
502	
503	  As already described above, pin groups are in turn self-descriptive, so
504	  the core will retrieve the actual pin range in a certain group from the
505	  driver.
506	
507	- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
508	  device by the board file, device tree or similar machine setup configuration
509	  mechanism, similar to how regulators are connected to devices, usually by
510	  name. Defining a pin controller, function and group thus uniquely identify
511	  the set of pins to be used by a certain device. (If only one possible group
512	  of pins is available for the function, no group name need to be supplied -
513	  the core will simply select the first and only group available.)
514	
515	  In the example case we can define that this particular machine shall
516	  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
517	  fi2c0 group gi2c0, on the primary pin controller, we get mappings
518	  like these:
519	
520	  {
521	    {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
522	    {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
523	  }
524	
525	  Every map must be assigned a state name, pin controller, device and
526	  function. The group is not compulsory - if it is omitted the first group
527	  presented by the driver as applicable for the function will be selected,
528	  which is useful for simple cases.
529	
530	  It is possible to map several groups to the same combination of device,
531	  pin controller and function. This is for cases where a certain function on
532	  a certain pin controller may use different sets of pins in different
533	  configurations.
534	
535	- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
536	  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
537	  other device mux setting or GPIO pin request has already taken your physical
538	  pin, you will be denied the use of it. To get (activate) a new setting, the
539	  old one has to be put (deactivated) first.
540	
541	Sometimes the documentation and hardware registers will be oriented around
542	pads (or "fingers") rather than pins - these are the soldering surfaces on the
543	silicon inside the package, and may or may not match the actual number of
544	pins/balls underneath the capsule. Pick some enumeration that makes sense to
545	you. Define enumerators only for the pins you can control if that makes sense.
546	
547	Assumptions:
548	
549	We assume that the number of possible function maps to pin groups is limited by
550	the hardware. I.e. we assume that there is no system where any function can be
551	mapped to any pin, like in a phone exchange. So the available pin groups for
552	a certain function will be limited to a few choices (say up to eight or so),
553	not hundreds or any amount of choices. This is the characteristic we have found
554	by inspecting available pinmux hardware, and a necessary assumption since we
555	expect pinmux drivers to present *all* possible function vs pin group mappings
556	to the subsystem.
557	
558	
559	Pinmux drivers
560	==============
561	
562	The pinmux core takes care of preventing conflicts on pins and calling
563	the pin controller driver to execute different settings.
564	
565	It is the responsibility of the pinmux driver to impose further restrictions
566	(say for example infer electronic limitations due to load, etc.) to determine
567	whether or not the requested function can actually be allowed, and in case it
568	is possible to perform the requested mux setting, poke the hardware so that
569	this happens.
570	
571	Pinmux drivers are required to supply a few callback functions, some are
572	optional. Usually the set_mux() function is implemented, writing values into
573	some certain registers to activate a certain mux setting for a certain pin.
574	
575	A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
576	into some register named MUX to select a certain function with a certain
577	group of pins would work something like this:
578	
579	#include <linux/pinctrl/pinctrl.h>
580	#include <linux/pinctrl/pinmux.h>
581	
582	struct foo_group {
583		const char *name;
584		const unsigned int *pins;
585		const unsigned num_pins;
586	};
587	
588	static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
589	static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
590	static const unsigned i2c0_pins[] = { 24, 25 };
591	static const unsigned mmc0_1_pins[] = { 56, 57 };
592	static const unsigned mmc0_2_pins[] = { 58, 59 };
593	static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
594	
595	static const struct foo_group foo_groups[] = {
596		{
597			.name = "spi0_0_grp",
598			.pins = spi0_0_pins,
599			.num_pins = ARRAY_SIZE(spi0_0_pins),
600		},
601		{
602			.name = "spi0_1_grp",
603			.pins = spi0_1_pins,
604			.num_pins = ARRAY_SIZE(spi0_1_pins),
605		},
606		{
607			.name = "i2c0_grp",
608			.pins = i2c0_pins,
609			.num_pins = ARRAY_SIZE(i2c0_pins),
610		},
611		{
612			.name = "mmc0_1_grp",
613			.pins = mmc0_1_pins,
614			.num_pins = ARRAY_SIZE(mmc0_1_pins),
615		},
616		{
617			.name = "mmc0_2_grp",
618			.pins = mmc0_2_pins,
619			.num_pins = ARRAY_SIZE(mmc0_2_pins),
620		},
621		{
622			.name = "mmc0_3_grp",
623			.pins = mmc0_3_pins,
624			.num_pins = ARRAY_SIZE(mmc0_3_pins),
625		},
626	};
627	
628	
629	static int foo_get_groups_count(struct pinctrl_dev *pctldev)
630	{
631		return ARRAY_SIZE(foo_groups);
632	}
633	
634	static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
635					       unsigned selector)
636	{
637		return foo_groups[selector].name;
638	}
639	
640	static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
641				       unsigned ** const pins,
642				       unsigned * const num_pins)
643	{
644		*pins = (unsigned *) foo_groups[selector].pins;
645		*num_pins = foo_groups[selector].num_pins;
646		return 0;
647	}
648	
649	static struct pinctrl_ops foo_pctrl_ops = {
650		.get_groups_count = foo_get_groups_count,
651		.get_group_name = foo_get_group_name,
652		.get_group_pins = foo_get_group_pins,
653	};
654	
655	struct foo_pmx_func {
656		const char *name;
657		const char * const *groups;
658		const unsigned num_groups;
659	};
660	
661	static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
662	static const char * const i2c0_groups[] = { "i2c0_grp" };
663	static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
664						"mmc0_3_grp" };
665	
666	static const struct foo_pmx_func foo_functions[] = {
667		{
668			.name = "spi0",
669			.groups = spi0_groups,
670			.num_groups = ARRAY_SIZE(spi0_groups),
671		},
672		{
673			.name = "i2c0",
674			.groups = i2c0_groups,
675			.num_groups = ARRAY_SIZE(i2c0_groups),
676		},
677		{
678			.name = "mmc0",
679			.groups = mmc0_groups,
680			.num_groups = ARRAY_SIZE(mmc0_groups),
681		},
682	};
683	
684	static int foo_get_functions_count(struct pinctrl_dev *pctldev)
685	{
686		return ARRAY_SIZE(foo_functions);
687	}
688	
689	static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
690	{
691		return foo_functions[selector].name;
692	}
693	
694	static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
695				  const char * const **groups,
696				  unsigned * const num_groups)
697	{
698		*groups = foo_functions[selector].groups;
699		*num_groups = foo_functions[selector].num_groups;
700		return 0;
701	}
702	
703	static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
704			unsigned group)
705	{
706		u8 regbit = (1 << selector + group);
707	
708		writeb((readb(MUX)|regbit), MUX)
709		return 0;
710	}
711	
712	static struct pinmux_ops foo_pmxops = {
713		.get_functions_count = foo_get_functions_count,
714		.get_function_name = foo_get_fname,
715		.get_function_groups = foo_get_groups,
716		.set_mux = foo_set_mux,
717	};
718	
719	/* Pinmux operations are handled by some pin controller */
720	static struct pinctrl_desc foo_desc = {
721		...
722		.pctlops = &foo_pctrl_ops,
723		.pmxops = &foo_pmxops,
724	};
725	
726	In the example activating muxing 0 and 1 at the same time setting bits
727	0 and 1, uses one pin in common so they would collide.
728	
729	The beauty of the pinmux subsystem is that since it keeps track of all
730	pins and who is using them, it will already have denied an impossible
731	request like that, so the driver does not need to worry about such
732	things - when it gets a selector passed in, the pinmux subsystem makes
733	sure no other device or GPIO assignment is already using the selected
734	pins. Thus bits 0 and 1 in the control register will never be set at the
735	same time.
736	
737	All the above functions are mandatory to implement for a pinmux driver.
738	
739	
740	Pin control interaction with the GPIO subsystem
741	===============================================
742	
743	Note that the following implies that the use case is to use a certain pin
744	from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
745	and similar functions. There are cases where you may be using something
746	that your datasheet calls "GPIO mode", but actually is just an electrical
747	configuration for a certain device. See the section below named
748	"GPIO mode pitfalls" for more details on this scenario.
749	
750	The public pinmux API contains two functions named pinctrl_request_gpio()
751	and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
752	gpiolib-based drivers as part of their gpio_request() and
753	gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
754	shall only be called from within respective gpio_direction_[input|output]
755	gpiolib implementation.
756	
757	NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
758	controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
759	that driver request proper muxing and other control for its pins.
760	
761	The function list could become long, especially if you can convert every
762	individual pin into a GPIO pin independent of any other pins, and then try
763	the approach to define every pin as a function.
764	
765	In this case, the function array would become 64 entries for each GPIO
766	setting and then the device functions.
767	
768	For this reason there are two functions a pin control driver can implement
769	to enable only GPIO on an individual pin: .gpio_request_enable() and
770	.gpio_disable_free().
771	
772	This function will pass in the affected GPIO range identified by the pin
773	controller core, so you know which GPIO pins are being affected by the request
774	operation.
775	
776	If your driver needs to have an indication from the framework of whether the
777	GPIO pin shall be used for input or output you can implement the
778	.gpio_set_direction() function. As described this shall be called from the
779	gpiolib driver and the affected GPIO range, pin offset and desired direction
780	will be passed along to this function.
781	
782	Alternatively to using these special functions, it is fully allowed to use
783	named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
784	obtain the function "gpioN" where "N" is the global GPIO pin number if no
785	special GPIO-handler is registered.
786	
787	
788	GPIO mode pitfalls
789	==================
790	
791	Due to the naming conventions used by hardware engineers, where "GPIO"
792	is taken to mean different things than what the kernel does, the developer
793	may be confused by a datasheet talking about a pin being possible to set
794	into "GPIO mode". It appears that what hardware engineers mean with
795	"GPIO mode" is not necessarily the use case that is implied in the kernel
796	interface <linux/gpio.h>: a pin that you grab from kernel code and then
797	either listen for input or drive high/low to assert/deassert some
798	external line.
799	
800	Rather hardware engineers think that "GPIO mode" means that you can
801	software-control a few electrical properties of the pin that you would
802	not be able to control if the pin was in some other mode, such as muxed in
803	for a device.
804	
805	The GPIO portions of a pin and its relation to a certain pin controller
806	configuration and muxing logic can be constructed in several ways. Here
807	are two examples:
808	
809	(A)
810	                       pin config
811	                       logic regs
812	                       |               +- SPI
813	     Physical pins --- pad --- pinmux -+- I2C
814	                               |       +- mmc
815	                               |       +- GPIO
816	                               pin
817	                               multiplex
818	                               logic regs
819	
820	Here some electrical properties of the pin can be configured no matter
821	whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
822	pin, you can also drive it high/low from "GPIO" registers.
823	Alternatively, the pin can be controlled by a certain peripheral, while
824	still applying desired pin config properties. GPIO functionality is thus
825	orthogonal to any other device using the pin.
826	
827	In this arrangement the registers for the GPIO portions of the pin controller,
828	or the registers for the GPIO hardware module are likely to reside in a
829	separate memory range only intended for GPIO driving, and the register
830	range dealing with pin config and pin multiplexing get placed into a
831	different memory range and a separate section of the data sheet.
832	
833	(B)
834	
835	                       pin config
836	                       logic regs
837	                       |               +- SPI
838	     Physical pins --- pad --- pinmux -+- I2C
839	                       |       |       +- mmc
840	                       |       |
841	                       GPIO    pin
842	                               multiplex
843	                               logic regs
844	
845	In this arrangement, the GPIO functionality can always be enabled, such that
846	e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
847	pulsed out. It is likely possible to disrupt the traffic on the pin by doing
848	wrong things on the GPIO block, as it is never really disconnected. It is
849	possible that the GPIO, pin config and pin multiplex registers are placed into
850	the same memory range and the same section of the data sheet, although that
851	need not be the case.
852	
853	From a kernel point of view, however, these are different aspects of the
854	hardware and shall be put into different subsystems:
855	
856	- Registers (or fields within registers) that control electrical
857	  properties of the pin such as biasing and drive strength should be
858	  exposed through the pinctrl subsystem, as "pin configuration" settings.
859	
860	- Registers (or fields within registers) that control muxing of signals
861	  from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
862	  be exposed through the pinctrl subsystem, as mux functions.
863	
864	- Registers (or fields within registers) that control GPIO functionality
865	  such as setting a GPIO's output value, reading a GPIO's input value, or
866	  setting GPIO pin direction should be exposed through the GPIO subsystem,
867	  and if they also support interrupt capabilities, through the irqchip
868	  abstraction.
869	
870	Depending on the exact HW register design, some functions exposed by the
871	GPIO subsystem may call into the pinctrl subsystem in order to
872	co-ordinate register settings across HW modules. In particular, this may
873	be needed for HW with separate GPIO and pin controller HW modules, where
874	e.g. GPIO direction is determined by a register in the pin controller HW
875	module rather than the GPIO HW module.
876	
877	Electrical properties of the pin such as biasing and drive strength
878	may be placed at some pin-specific register in all cases or as part
879	of the GPIO register in case (B) especially. This doesn't mean that such
880	properties necessarily pertain to what the Linux kernel calls "GPIO".
881	
882	Example: a pin is usually muxed in to be used as a UART TX line. But during
883	system sleep, we need to put this pin into "GPIO mode" and ground it.
884	
885	If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
886	to think that you need to come up with something really complex, that the
887	pin shall be used for UART TX and GPIO at the same time, that you will grab
888	a pin control handle and set it to a certain state to enable UART TX to be
889	muxed in, then twist it over to GPIO mode and use gpio_direction_output()
890	to drive it low during sleep, then mux it over to UART TX again when you
891	wake up and maybe even gpio_request/gpio_free as part of this cycle. This
892	all gets very complicated.
893	
894	The solution is to not think that what the datasheet calls "GPIO mode"
895	has to be handled by the <linux/gpio.h> interface. Instead view this as
896	a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
897	and you find this in the documentation:
898	
899	  PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
900	     1 to indicate high level, argument 0 to indicate low level.
901	
902	So it is perfectly possible to push a pin into "GPIO mode" and drive the
903	line low as part of the usual pin control map. So for example your UART
904	driver may look like this:
905	
906	#include <linux/pinctrl/consumer.h>
907	
908	struct pinctrl          *pinctrl;
909	struct pinctrl_state    *pins_default;
910	struct pinctrl_state    *pins_sleep;
911	
912	pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
913	pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
914	
915	/* Normal mode */
916	retval = pinctrl_select_state(pinctrl, pins_default);
917	/* Sleep mode */
918	retval = pinctrl_select_state(pinctrl, pins_sleep);
919	
920	And your machine configuration may look like this:
921	--------------------------------------------------
922	
923	static unsigned long uart_default_mode[] = {
924	    PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
925	};
926	
927	static unsigned long uart_sleep_mode[] = {
928	    PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
929	};
930	
931	static struct pinctrl_map pinmap[] __initdata = {
932	    PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
933	                      "u0_group", "u0"),
934	    PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
935	                        "UART_TX_PIN", uart_default_mode),
936	    PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
937	                      "u0_group", "gpio-mode"),
938	    PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
939	                        "UART_TX_PIN", uart_sleep_mode),
940	};
941	
942	foo_init(void) {
943	    pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
944	}
945	
946	Here the pins we want to control are in the "u0_group" and there is some
947	function called "u0" that can be enabled on this group of pins, and then
948	everything is UART business as usual. But there is also some function
949	named "gpio-mode" that can be mapped onto the same pins to move them into
950	GPIO mode.
951	
952	This will give the desired effect without any bogus interaction with the
953	GPIO subsystem. It is just an electrical configuration used by that device
954	when going to sleep, it might imply that the pin is set into something the
955	datasheet calls "GPIO mode", but that is not the point: it is still used
956	by that UART device to control the pins that pertain to that very UART
957	driver, putting them into modes needed by the UART. GPIO in the Linux
958	kernel sense are just some 1-bit line, and is a different use case.
959	
960	How the registers are poked to attain the push or pull, and output low
961	configuration and the muxing of the "u0" or "gpio-mode" group onto these
962	pins is a question for the driver.
963	
964	Some datasheets will be more helpful and refer to the "GPIO mode" as
965	"low power mode" rather than anything to do with GPIO. This often means
966	the same thing electrically speaking, but in this latter case the
967	software engineers will usually quickly identify that this is some
968	specific muxing or configuration rather than anything related to the GPIO
969	API.
970	
971	
972	Board/machine configuration
973	==================================
974	
975	Boards and machines define how a certain complete running system is put
976	together, including how GPIOs and devices are muxed, how regulators are
977	constrained and how the clock tree looks. Of course pinmux settings are also
978	part of this.
979	
980	A pin controller configuration for a machine looks pretty much like a simple
981	regulator configuration, so for the example array above we want to enable i2c
982	and spi on the second function mapping:
983	
984	#include <linux/pinctrl/machine.h>
985	
986	static const struct pinctrl_map mapping[] __initconst = {
987		{
988			.dev_name = "foo-spi.0",
989			.name = PINCTRL_STATE_DEFAULT,
990			.type = PIN_MAP_TYPE_MUX_GROUP,
991			.ctrl_dev_name = "pinctrl-foo",
992			.data.mux.function = "spi0",
993		},
994		{
995			.dev_name = "foo-i2c.0",
996			.name = PINCTRL_STATE_DEFAULT,
997			.type = PIN_MAP_TYPE_MUX_GROUP,
998			.ctrl_dev_name = "pinctrl-foo",
999			.data.mux.function = "i2c0",
1000		},
1001		{
1002			.dev_name = "foo-mmc.0",
1003			.name = PINCTRL_STATE_DEFAULT,
1004			.type = PIN_MAP_TYPE_MUX_GROUP,
1005			.ctrl_dev_name = "pinctrl-foo",
1006			.data.mux.function = "mmc0",
1007		},
1008	};
1009	
1010	The dev_name here matches to the unique device name that can be used to look
1011	up the device struct (just like with clockdev or regulators). The function name
1012	must match a function provided by the pinmux driver handling this pin range.
1013	
1014	As you can see we may have several pin controllers on the system and thus
1015	we need to specify which one of them contains the functions we wish to map.
1016	
1017	You register this pinmux mapping to the pinmux subsystem by simply:
1018	
1019	       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
1020	
1021	Since the above construct is pretty common there is a helper macro to make
1022	it even more compact which assumes you want to use pinctrl-foo and position
1023	0 for mapping, for example:
1024	
1025	static struct pinctrl_map mapping[] __initdata = {
1026		PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1027	};
1028	
1029	The mapping table may also contain pin configuration entries. It's common for
1030	each pin/group to have a number of configuration entries that affect it, so
1031	the table entries for configuration reference an array of config parameters
1032	and values. An example using the convenience macros is shown below:
1033	
1034	static unsigned long i2c_grp_configs[] = {
1035		FOO_PIN_DRIVEN,
1036		FOO_PIN_PULLUP,
1037	};
1038	
1039	static unsigned long i2c_pin_configs[] = {
1040		FOO_OPEN_COLLECTOR,
1041		FOO_SLEW_RATE_SLOW,
1042	};
1043	
1044	static struct pinctrl_map mapping[] __initdata = {
1045		PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
1046		PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1047		PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1048		PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1049	};
1050	
1051	Finally, some devices expect the mapping table to contain certain specific
1052	named states. When running on hardware that doesn't need any pin controller
1053	configuration, the mapping table must still contain those named states, in
1054	order to explicitly indicate that the states were provided and intended to
1055	be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1056	a named state without causing any pin controller to be programmed:
1057	
1058	static struct pinctrl_map mapping[] __initdata = {
1059		PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1060	};
1061	
1062	
1063	Complex mappings
1064	================
1065	
1066	As it is possible to map a function to different groups of pins an optional
1067	.group can be specified like this:
1068	
1069	...
1070	{
1071		.dev_name = "foo-spi.0",
1072		.name = "spi0-pos-A",
1073		.type = PIN_MAP_TYPE_MUX_GROUP,
1074		.ctrl_dev_name = "pinctrl-foo",
1075		.function = "spi0",
1076		.group = "spi0_0_grp",
1077	},
1078	{
1079		.dev_name = "foo-spi.0",
1080		.name = "spi0-pos-B",
1081		.type = PIN_MAP_TYPE_MUX_GROUP,
1082		.ctrl_dev_name = "pinctrl-foo",
1083		.function = "spi0",
1084		.group = "spi0_1_grp",
1085	},
1086	...
1087	
1088	This example mapping is used to switch between two positions for spi0 at
1089	runtime, as described further below under the heading "Runtime pinmuxing".
1090	
1091	Further it is possible for one named state to affect the muxing of several
1092	groups of pins, say for example in the mmc0 example above, where you can
1093	additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1094	three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1095	case), we define a mapping like this:
1096	
1097	...
1098	{
1099		.dev_name = "foo-mmc.0",
1100		.name = "2bit"
1101		.type = PIN_MAP_TYPE_MUX_GROUP,
1102		.ctrl_dev_name = "pinctrl-foo",
1103		.function = "mmc0",
1104		.group = "mmc0_1_grp",
1105	},
1106	{
1107		.dev_name = "foo-mmc.0",
1108		.name = "4bit"
1109		.type = PIN_MAP_TYPE_MUX_GROUP,
1110		.ctrl_dev_name = "pinctrl-foo",
1111		.function = "mmc0",
1112		.group = "mmc0_1_grp",
1113	},
1114	{
1115		.dev_name = "foo-mmc.0",
1116		.name = "4bit"
1117		.type = PIN_MAP_TYPE_MUX_GROUP,
1118		.ctrl_dev_name = "pinctrl-foo",
1119		.function = "mmc0",
1120		.group = "mmc0_2_grp",
1121	},
1122	{
1123		.dev_name = "foo-mmc.0",
1124		.name = "8bit"
1125		.type = PIN_MAP_TYPE_MUX_GROUP,
1126		.ctrl_dev_name = "pinctrl-foo",
1127		.function = "mmc0",
1128		.group = "mmc0_1_grp",
1129	},
1130	{
1131		.dev_name = "foo-mmc.0",
1132		.name = "8bit"
1133		.type = PIN_MAP_TYPE_MUX_GROUP,
1134		.ctrl_dev_name = "pinctrl-foo",
1135		.function = "mmc0",
1136		.group = "mmc0_2_grp",
1137	},
1138	{
1139		.dev_name = "foo-mmc.0",
1140		.name = "8bit"
1141		.type = PIN_MAP_TYPE_MUX_GROUP,
1142		.ctrl_dev_name = "pinctrl-foo",
1143		.function = "mmc0",
1144		.group = "mmc0_3_grp",
1145	},
1146	...
1147	
1148	The result of grabbing this mapping from the device with something like
1149	this (see next paragraph):
1150	
1151		p = devm_pinctrl_get(dev);
1152		s = pinctrl_lookup_state(p, "8bit");
1153		ret = pinctrl_select_state(p, s);
1154	
1155	or more simply:
1156	
1157		p = devm_pinctrl_get_select(dev, "8bit");
1158	
1159	Will be that you activate all the three bottom records in the mapping at
1160	once. Since they share the same name, pin controller device, function and
1161	device, and since we allow multiple groups to match to a single device, they
1162	all get selected, and they all get enabled and disable simultaneously by the
1163	pinmux core.
1164	
1165	
1166	Pin control requests from drivers
1167	=================================
1168	
1169	When a device driver is about to probe the device core will automatically
1170	attempt to issue pinctrl_get_select_default() on these devices.
1171	This way driver writers do not need to add any of the boilerplate code
1172	of the type found below. However when doing fine-grained state selection
1173	and not using the "default" state, you may have to do some device driver
1174	handling of the pinctrl handles and states.
1175	
1176	So if you just want to put the pins for a certain device into the default
1177	state and be done with it, there is nothing you need to do besides
1178	providing the proper mapping table. The device core will take care of
1179	the rest.
1180	
1181	Generally it is discouraged to let individual drivers get and enable pin
1182	control. So if possible, handle the pin control in platform code or some other
1183	place where you have access to all the affected struct device * pointers. In
1184	some cases where a driver needs to e.g. switch between different mux mappings
1185	at runtime this is not possible.
1186	
1187	A typical case is if a driver needs to switch bias of pins from normal
1188	operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1189	PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1190	current in sleep mode.
1191	
1192	A driver may request a certain control state to be activated, usually just the
1193	default state like this:
1194	
1195	#include <linux/pinctrl/consumer.h>
1196	
1197	struct foo_state {
1198	       struct pinctrl *p;
1199	       struct pinctrl_state *s;
1200	       ...
1201	};
1202	
1203	foo_probe()
1204	{
1205		/* Allocate a state holder named "foo" etc */
1206		struct foo_state *foo = ...;
1207	
1208		foo->p = devm_pinctrl_get(&device);
1209		if (IS_ERR(foo->p)) {
1210			/* FIXME: clean up "foo" here */
1211			return PTR_ERR(foo->p);
1212		}
1213	
1214		foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1215		if (IS_ERR(foo->s)) {
1216			/* FIXME: clean up "foo" here */
1217			return PTR_ERR(s);
1218		}
1219	
1220		ret = pinctrl_select_state(foo->s);
1221		if (ret < 0) {
1222			/* FIXME: clean up "foo" here */
1223			return ret;
1224		}
1225	}
1226	
1227	This get/lookup/select/put sequence can just as well be handled by bus drivers
1228	if you don't want each and every driver to handle it and you know the
1229	arrangement on your bus.
1230	
1231	The semantics of the pinctrl APIs are:
1232	
1233	- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1234	  information for a given client device. It will allocate a struct from the
1235	  kernel memory to hold the pinmux state. All mapping table parsing or similar
1236	  slow operations take place within this API.
1237	
1238	- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1239	  to be called automatically on the retrieved pointer when the associated
1240	  device is removed. It is recommended to use this function over plain
1241	  pinctrl_get().
1242	
1243	- pinctrl_lookup_state() is called in process context to obtain a handle to a
1244	  specific state for a client device. This operation may be slow, too.
1245	
1246	- pinctrl_select_state() programs pin controller hardware according to the
1247	  definition of the state as given by the mapping table. In theory, this is a
1248	  fast-path operation, since it only involved blasting some register settings
1249	  into hardware. However, note that some pin controllers may have their
1250	  registers on a slow/IRQ-based bus, so client devices should not assume they
1251	  can call pinctrl_select_state() from non-blocking contexts.
1252	
1253	- pinctrl_put() frees all information associated with a pinctrl handle.
1254	
1255	- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1256	  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1257	  However, use of this function will be rare, due to the automatic cleanup
1258	  that will occur even without calling it.
1259	
1260	  pinctrl_get() must be paired with a plain pinctrl_put().
1261	  pinctrl_get() may not be paired with devm_pinctrl_put().
1262	  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1263	  devm_pinctrl_get() may not be paired with plain pinctrl_put().
1264	
1265	Usually the pin control core handled the get/put pair and call out to the
1266	device drivers bookkeeping operations, like checking available functions and
1267	the associated pins, whereas select_state pass on to the pin controller
1268	driver which takes care of activating and/or deactivating the mux setting by
1269	quickly poking some registers.
1270	
1271	The pins are allocated for your device when you issue the devm_pinctrl_get()
1272	call, after this you should be able to see this in the debugfs listing of all
1273	pins.
1274	
1275	NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1276	requested pinctrl handles, for example if the pinctrl driver has not yet
1277	registered. Thus make sure that the error path in your driver gracefully
1278	cleans up and is ready to retry the probing later in the startup process.
1279	
1280	
1281	Drivers needing both pin control and GPIOs
1282	==========================================
1283	
1284	Again, it is discouraged to let drivers lookup and select pin control states
1285	themselves, but again sometimes this is unavoidable.
1286	
1287	So say that your driver is fetching its resources like this:
1288	
1289	#include <linux/pinctrl/consumer.h>
1290	#include <linux/gpio.h>
1291	
1292	struct pinctrl *pinctrl;
1293	int gpio;
1294	
1295	pinctrl = devm_pinctrl_get_select_default(&dev);
1296	gpio = devm_gpio_request(&dev, 14, "foo");
1297	
1298	Here we first request a certain pin state and then request GPIO 14 to be
1299	used. If you're using the subsystems orthogonally like this, you should
1300	nominally always get your pinctrl handle and select the desired pinctrl
1301	state BEFORE requesting the GPIO. This is a semantic convention to avoid
1302	situations that can be electrically unpleasant, you will certainly want to
1303	mux in and bias pins in a certain way before the GPIO subsystems starts to
1304	deal with them.
1305	
1306	The above can be hidden: using the device core, the pinctrl core may be
1307	setting up the config and muxing for the pins right before the device is
1308	probing, nevertheless orthogonal to the GPIO subsystem.
1309	
1310	But there are also situations where it makes sense for the GPIO subsystem
1311	to communicate directly with the pinctrl subsystem, using the latter as a
1312	back-end. This is when the GPIO driver may call out to the functions
1313	described in the section "Pin control interaction with the GPIO subsystem"
1314	above. This only involves per-pin multiplexing, and will be completely
1315	hidden behind the gpio_*() function namespace. In this case, the driver
1316	need not interact with the pin control subsystem at all.
1317	
1318	If a pin control driver and a GPIO driver is dealing with the same pins
1319	and the use cases involve multiplexing, you MUST implement the pin controller
1320	as a back-end for the GPIO driver like this, unless your hardware design
1321	is such that the GPIO controller can override the pin controller's
1322	multiplexing state through hardware without the need to interact with the
1323	pin control system.
1324	
1325	
1326	System pin control hogging
1327	==========================
1328	
1329	Pin control map entries can be hogged by the core when the pin controller
1330	is registered. This means that the core will attempt to call pinctrl_get(),
1331	lookup_state() and select_state() on it immediately after the pin control
1332	device has been registered.
1333	
1334	This occurs for mapping table entries where the client device name is equal
1335	to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1336	
1337	{
1338		.dev_name = "pinctrl-foo",
1339		.name = PINCTRL_STATE_DEFAULT,
1340		.type = PIN_MAP_TYPE_MUX_GROUP,
1341		.ctrl_dev_name = "pinctrl-foo",
1342		.function = "power_func",
1343	},
1344	
1345	Since it may be common to request the core to hog a few always-applicable
1346	mux settings on the primary pin controller, there is a convenience macro for
1347	this:
1348	
1349	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1350	
1351	This gives the exact same result as the above construction.
1352	
1353	
1354	Runtime pinmuxing
1355	=================
1356	
1357	It is possible to mux a certain function in and out at runtime, say to move
1358	an SPI port from one set of pins to another set of pins. Say for example for
1359	spi0 in the example above, we expose two different groups of pins for the same
1360	function, but with different named in the mapping as described under
1361	"Advanced mapping" above. So that for an SPI device, we have two states named
1362	"pos-A" and "pos-B".
1363	
1364	This snippet first initializes a state object for both groups (in foo_probe()),
1365	then muxes the function in the pins defined by group A, and finally muxes it in
1366	on the pins defined by group B:
1367	
1368	#include <linux/pinctrl/consumer.h>
1369	
1370	struct pinctrl *p;
1371	struct pinctrl_state *s1, *s2;
1372	
1373	foo_probe()
1374	{
1375		/* Setup */
1376		p = devm_pinctrl_get(&device);
1377		if (IS_ERR(p))
1378			...
1379	
1380		s1 = pinctrl_lookup_state(foo->p, "pos-A");
1381		if (IS_ERR(s1))
1382			...
1383	
1384		s2 = pinctrl_lookup_state(foo->p, "pos-B");
1385		if (IS_ERR(s2))
1386			...
1387	}
1388	
1389	foo_switch()
1390	{
1391		/* Enable on position A */
1392		ret = pinctrl_select_state(s1);
1393		if (ret < 0)
1394		    ...
1395	
1396		...
1397	
1398		/* Enable on position B */
1399		ret = pinctrl_select_state(s2);
1400		if (ret < 0)
1401		    ...
1402	
1403		...
1404	}
1405	
1406	The above has to be done from process context. The reservation of the pins
1407	will be done when the state is activated, so in effect one specific pin
1408	can be used by different functions at different times on a running system.
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