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Documentation / devicetree / bindings / arm / gic.txt




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Based on kernel version 4.0. Page generated on 2015-04-14 21:20 EST.

1	* ARM Generic Interrupt Controller
2	
3	ARM SMP cores are often associated with a GIC, providing per processor
4	interrupts (PPI), shared processor interrupts (SPI) and software
5	generated interrupts (SGI).
6	
7	Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8	Secondary GICs are cascaded into the upward interrupt controller and do not
9	have PPIs or SGIs.
10	
11	Main node required properties:
12	
13	- compatible : should be one of:
14		"arm,gic-400"
15		"arm,cortex-a15-gic"
16		"arm,cortex-a9-gic"
17		"arm,cortex-a7-gic"
18		"arm,arm11mp-gic"
19		"brcm,brahma-b15-gic"
20		"arm,arm1176jzf-devchip-gic"
21	- interrupt-controller : Identifies the node as an interrupt controller
22	- #interrupt-cells : Specifies the number of cells needed to encode an
23	  interrupt source.  The type shall be a <u32> and the value shall be 3.
24	
25	  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
26	  interrupts.
27	
28	  The 2nd cell contains the interrupt number for the interrupt type.
29	  SPI interrupts are in the range [0-987].  PPI interrupts are in the
30	  range [0-15].
31	
32	  The 3rd cell is the flags, encoded as follows:
33		bits[3:0] trigger type and level flags.
34			1 = low-to-high edge triggered
35			2 = high-to-low edge triggered (invalid for SPIs)
36			4 = active high level-sensitive
37			8 = active low level-sensitive (invalid for SPIs).
38		bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
39		the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
40		the interrupt is wired to that CPU.  Only valid for PPI interrupts.
41		Also note that the configurability of PPI interrupts is IMPLEMENTATION
42		DEFINED and as such not guaranteed to be present (most SoC available
43		in 2014 seem to ignore the setting of this flag and use the hardware
44		default value).
45	
46	- reg : Specifies base physical address(s) and size of the GIC registers. The
47	  first region is the GIC distributor register base and size. The 2nd region is
48	  the GIC cpu interface register base and size.
49	
50	Optional
51	- interrupts	: Interrupt source of the parent interrupt controller on
52	  secondary GICs, or VGIC maintenance interrupt on primary GIC (see
53	  below).
54	
55	- cpu-offset	: per-cpu offset within the distributor and cpu interface
56	  regions, used when the GIC doesn't have banked registers. The offset is
57	  cpu-offset * cpu-nr.
58	
59	- arm,routable-irqs : Total number of gic irq inputs which are not directly
60			  connected from the peripherals, but are routed dynamically
61			  by a crossbar/multiplexer preceding the GIC. The GIC irq
62			  input line is assigned dynamically when the corresponding
63			  peripheral's crossbar line is mapped.
64	Example:
65	
66		intc: interrupt-controller@fff11000 {
67			compatible = "arm,cortex-a9-gic";
68			#interrupt-cells = <3>;
69			#address-cells = <1>;
70			interrupt-controller;
71			arm,routable-irqs = <160>;
72			reg = <0xfff11000 0x1000>,
73			      <0xfff10100 0x100>;
74		};
75	
76	
77	* GIC virtualization extensions (VGIC)
78	
79	For ARM cores that support the virtualization extensions, additional
80	properties must be described (they only exist if the GIC is the
81	primary interrupt controller).
82	
83	Required properties:
84	
85	- reg : Additional regions specifying the base physical address and
86	  size of the VGIC registers. The first additional region is the GIC
87	  virtual interface control register base and size. The 2nd additional
88	  region is the GIC virtual cpu interface register base and size.
89	
90	- interrupts : VGIC maintenance interrupt.
91	
92	Example:
93	
94		interrupt-controller@2c001000 {
95			compatible = "arm,cortex-a15-gic";
96			#interrupt-cells = <3>;
97			interrupt-controller;
98			reg = <0x2c001000 0x1000>,
99			      <0x2c002000 0x1000>,
100			      <0x2c004000 0x2000>,
101			      <0x2c006000 0x2000>;
102			interrupts = <1 9 0xf04>;
103		};
104	
105	
106	* GICv2m extension for MSI/MSI-x support (Optional)
107	
108	Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
109	This is enabled by specifying v2m sub-node(s).
110	
111	Required properties:
112	
113	- compatible	    : The value here should contain "arm,gic-v2m-frame".
114	
115	- msi-controller    : Identifies the node as an MSI controller.
116	
117	- reg		    : GICv2m MSI interface register base and size
118	
119	Optional properties:
120	
121	- arm,msi-base-spi  : When the MSI_TYPER register contains an incorrect
122	  		      value, this property should contain the SPI base of
123			      the MSI frame, overriding the HW value.
124	
125	- arm,msi-num-spis  : When the MSI_TYPER register contains an incorrect
126	  		      value, this property should contain the number of
127			      SPIs assigned to the frame, overriding the HW value.
128	
129	Example:
130	
131		interrupt-controller@e1101000 {
132			compatible = "arm,gic-400";
133			#interrupt-cells = <3>;
134			#address-cells = <2>;
135			#size-cells = <2>;
136			interrupt-controller;
137			interrupts = <1 8 0xf04>;
138			ranges = <0 0 0 0xe1100000 0 0x100000>;
139			reg = <0x0 0xe1110000 0 0x01000>,
140			      <0x0 0xe112f000 0 0x02000>,
141			      <0x0 0xe1140000 0 0x10000>,
142			      <0x0 0xe1160000 0 0x10000>;
143			v2m0: v2m@0x8000 {
144				compatible = "arm,gic-v2m-frame";
145				msi-controller;
146				reg = <0x0 0x80000 0 0x1000>;
147			};
148	
149			....
150	
151			v2mN: v2m@0x9000 {
152				compatible = "arm,gic-v2m-frame";
153				msi-controller;
154				reg = <0x0 0x90000 0 0x1000>;
155			};
156		};
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